Line 1... |
Line 1... |
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is
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sourced by a combinatorial pin. This is not good design practice. Use the CE
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
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pin to control the loading of data into the flip-flop.
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pin to control the loading of data into the flip-flop.
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is
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sourced by a combinatorial pin. This is not good design practice. Use the CE
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
pin to control the loading of data into the flip-flop.
|
pin to control the loading of data into the flip-flop.
|
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is
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sourced by a combinatorial pin. This is not good design practice. Use the CE
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
pin to control the loading of data into the flip-flop.
|
pin to control the loading of data into the flip-flop.
|
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is
|
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
pin to control the loading of data into the flip-flop.
|
pin to control the loading of data into the flip-flop.
|
DRC detected 0 errors and 4 warnings.
|
WARNING:PhysDesignRules:812 - Dangling pin on
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block::
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6A>.
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WARNING:PhysDesignRules:812 - Dangling pin on
|
|
block::
|
|
6A>.
|
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WARNING:PhysDesignRules:812 - Dangling pin on
|
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block::
|
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6A>.
|
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DRC detected 0 errors and 7 warnings.
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