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Release 8.2.02i par I.33
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Release 8.2.02i par I.33
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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SCOTT-H-PC:: Sat Nov 11 00:49:50 2006
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SCOTT-H-PC:: Wed Nov 15 08:50:34 2006
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par -w -intstyle ise -ol std -t 1 testbench_map.ncd testbench.ncd testbench.pcf
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par -w -intstyle ise -ol std -t 1 testbench_map.ncd testbench.ncd testbench.pcf
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Constraints file: testbench.pcf.
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Constraints file: testbench.pcf.
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Line 26... |
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Number of BUFGMUXs 2 out of 8 25%
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Number of BUFGMUXs 2 out of 8 25%
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Number of External IOBs 54 out of 173 31%
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Number of External IOBs 54 out of 173 31%
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Number of LOCed IOBs 46 out of 54 85%
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Number of LOCed IOBs 46 out of 54 85%
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Number of MULT18X18s 1 out of 24 4%
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Number of MULT18X18s 2 out of 24 8%
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Number of RAMB16s 3 out of 24 12%
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Number of RAMB16s 4 out of 24 16%
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Number of Slices 3312 out of 7680 43%
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Number of Slices 3458 out of 7680 45%
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Number of SLICEMs 964 out of 3840 25%
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Number of SLICEMs 958 out of 3840 24%
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Overall effort level (-ol): Standard
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Overall effort level (-ol): Standard
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Placer effort level (-pl): High
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Placer effort level (-pl): High
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Line 42... |
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Starting Placer
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Starting Placer
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Phase 1.1
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Phase 1.1
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Phase 1.1 (Checksum:996f21) REAL time: 11 secs
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Phase 1.1 (Checksum:9984aa) REAL time: 9 secs
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Phase 2.7
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Phase 2.7
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WARNING:Place:837 - Partially locked IO Bus is found.
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WARNING:Place:837 - Partially locked IO Bus is found.
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Following components of the bus are not locked:
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Following components of the bus are not locked:
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Comp: addr<15>
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Comp: addr<15>
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Line 58... |
Comp: addr<9>
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Comp: addr<9>
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Comp: addr<8>
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Comp: addr<8>
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INFO:Place:834 - Only a subset of IOs are locked. Out of 54 IOs, 46 are locked and 8 are not locked. If you would like
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INFO:Place:834 - Only a subset of IOs are locked. Out of 54 IOs, 46 are locked and 8 are not locked. If you would like
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to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 2 (or more).
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to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 2 (or more).
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Phase 2.7 (Checksum:1312cfe) REAL time: 11 secs
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Phase 2.7 (Checksum:1312cfe) REAL time: 10 secs
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Phase 3.31
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Phase 3.31
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Phase 3.31 (Checksum:1c9c37d) REAL time: 11 secs
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Phase 3.31 (Checksum:1c9c37d) REAL time: 10 secs
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Phase 4.2
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Phase 4.2
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.....
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.....
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...................
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...................
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Phase 4.2 (Checksum:98bdc7) REAL time: 22 secs
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Phase 4.2 (Checksum:98bdc7) REAL time: 18 secs
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Phase 5.3
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Phase 5.3
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Phase 5.3 (Checksum:2faf07b) REAL time: 22 secs
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Phase 5.3 (Checksum:2faf07b) REAL time: 18 secs
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Phase 6.5
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Phase 6.5
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Phase 6.5 (Checksum:39386fa) REAL time: 23 secs
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Phase 6.5 (Checksum:39386fa) REAL time: 19 secs
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Phase 7.8
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Phase 7.8
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.......................................................................................................................................................................................................................................
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.....................................................
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.........
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.....................................
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.............................................................................................
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...............................................................................................................................................................................
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..................
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.......
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............
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.......
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.....................................................................................................................................................................................................
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.....
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Phase 7.8 (Checksum:13e75c6) REAL time: 2 mins 56 secs
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Phase 7.8 (Checksum:1191c59) REAL time: 2 mins 2 secs
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Phase 8.5
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Phase 8.5
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Phase 8.5 (Checksum:4c4b3f8) REAL time: 2 mins 57 secs
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Phase 8.5 (Checksum:4c4b3f8) REAL time: 2 mins 2 secs
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Phase 9.18
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Phase 9.18
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Phase 9.18 (Checksum:55d4a77) REAL time: 4 mins 9 secs
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Phase 9.18 (Checksum:55d4a77) REAL time: 2 mins 53 secs
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Phase 10.5
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Phase 10.5
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Phase 10.5 (Checksum:5f5e0f6) REAL time: 4 mins 9 secs
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Phase 10.5 (Checksum:5f5e0f6) REAL time: 2 mins 53 secs
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Writing design to file testbench.ncd
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Writing design to file testbench.ncd
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Total REAL time to Placer completion: 4 mins 14 secs
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Total REAL time to Placer completion: 2 mins 57 secs
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Total CPU time to Placer completion: 3 mins 33 secs
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Total CPU time to Placer completion: 2 mins 51 secs
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Starting Router
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Starting Router
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Phase 1: 26804 unrouted; REAL time: 4 mins 14 secs
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Phase 1: 27686 unrouted; REAL time: 2 mins 57 secs
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Phase 2: 26061 unrouted; REAL time: 3 mins 6 secs
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Phase 3: 8086 unrouted; REAL time: 3 mins 13 secs
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Phase 2: 25251 unrouted; REAL time: 4 mins 27 secs
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Phase 4: 8086 unrouted; (44628) REAL time: 3 mins 13 secs
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Phase 3: 7585 unrouted; REAL time: 4 mins 37 secs
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Phase 5: 8305 unrouted; (0) REAL time: 3 mins 17 secs
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Phase 4: 7585 unrouted; (20316) REAL time: 4 mins 37 secs
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Phase 6: 0 unrouted; (12079) REAL time: 3 mins 42 secs
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Phase 5: 7586 unrouted; (0) REAL time: 4 mins 40 secs
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Phase 7: 0 unrouted; (12079) REAL time: 3 mins 45 secs
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Phase 6: 0 unrouted; (0) REAL time: 5 mins 11 secs
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Phase 8: 0 unrouted; (3768) REAL time: 4 mins
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Phase 7: 0 unrouted; (0) REAL time: 5 mins 15 secs
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Phase 9: 0 unrouted; (3768) REAL time: 4 mins 2 secs
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WARNING:Route:447 - CLK Net:reset_n_BUFGP may have excessive skew because
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WARNING:Route:447 - CLK Net:reset_n_BUFGP may have excessive skew because
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442 NON-CLK pins failed to route using a CLK template.
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463 NON-CLK pins failed to route using a CLK template.
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Total REAL time to Router completion: 5 mins 16 secs
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Total REAL time to Router completion: 4 mins 2 secs
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Total CPU time to Router completion: 4 mins 25 secs
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Total CPU time to Router completion: 3 mins 57 secs
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Partition Implementation Status
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Partition Implementation Status
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-------------------------------
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-------------------------------
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No Partitions were found in this design.
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No Partitions were found in this design.
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Line 142... |
**************************
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**************************
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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| clock_BUFGP | BUFGMUX3| No | 1338 | 0.485 | 1.185 |
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| clock_BUFGP | BUFGMUX3| No | 1384 | 0.436 | 1.139 |
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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| reset_n_BUFGP | BUFGMUX5| No | 458 | 0.200 | 0.960 |
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| reset_n_BUFGP | BUFGMUX5| No | 479 | 0.196 | 0.916 |
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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|select1/selectb/_and | | | | | |
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|select1/selectc/_and | | | | | |
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| 0000 | Local| | 7 | 0.166 | 2.998 |
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| 0000 | Local| | 7 | 0.008 | 2.121 |
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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|select1/selecta/_and | | | | | |
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|select1/selecta/_and | | | | | |
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| 0000 | Local| | 7 | 0.278 | 2.413 |
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| 0000 | Local| | 7 | 0.038 | 2.244 |
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+---------------------+--------------+------+------+------------+-------------+
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|select1/selectc/_and | | | | | |
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| 0000 | Local| | 7 | 0.025 | 2.148 |
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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|select1/selectd/_and | | | | | |
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|select1/selectd/_and | | | | | |
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| 0000 | Local| | 7 | 0.135 | 2.994 |
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| 0000 | Local| | 7 | 0.083 | 2.850 |
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+---------------------+--------------+------+------+------------+-------------+
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|select1/selectb/_and | | | | | |
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| 0000 | Local| | 7 | 0.061 | 2.289 |
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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* Net Skew is the difference between the minimum and maximum routing
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* Net Skew is the difference between the minimum and maximum routing
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only delays for the net. Note this is different from Clock Skew which
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only delays for the net. Note this is different from Clock Skew which
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is reported in TRCE timing report. Clock Skew is the difference between
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is reported in TRCE timing report. Clock Skew is the difference between
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Line 170... |
The Delay Summary Report
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The Delay Summary Report
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The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
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The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
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The AVERAGE CONNECTION DELAY for this design is: 2.358
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The AVERAGE CONNECTION DELAY for this design is: 2.329
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The MAXIMUM PIN DELAY IS: 10.245
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The MAXIMUM PIN DELAY IS: 10.680
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The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 8.763
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The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 9.230
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Listing Pin Delays by value: (nsec)
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Listing Pin Delays by value: (nsec)
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d < 2.00 < d < 4.00 < d < 6.00 < d < 8.00 < d < 11.00 d >= 11.00
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d < 2.00 < d < 4.00 < d < 6.00 < d < 8.00 < d < 11.00 d >= 11.00
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--------- --------- --------- --------- --------- ---------
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--------- --------- --------- --------- --------- ---------
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14013 8132 4035 824 140 0
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14637 7957 4563 746 81 0
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Timing Score: 0
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Timing Score: 0
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Asterisk (*) preceding a constraint indicates it was not met.
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Asterisk (*) preceding a constraint indicates it was not met.
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This may be due to a setup or hold violation.
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This may be due to a setup or hold violation.
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------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------
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Constraint | Requested | Actual | Logic | Absolute |Number of
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Constraint | Requested | Actual | Logic | Absolute |Number of
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| | | Levels | Slack |errors
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| | | Levels | Slack |errors
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------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net clo | N/A | 22.020ns | 10 | N/A | N/A
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Autotimespec constraint for clock net clo | N/A | 19.923ns | 9 | N/A | N/A
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ck_BUFGP | | | | |
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ck_BUFGP | | | | |
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------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------
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All constraints were met.
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All constraints were met.
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Line 203... |
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Generating Pad Report.
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Generating Pad Report.
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All signals are completely routed.
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All signals are completely routed.
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Total REAL time to PAR completion: 5 mins 26 secs
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Total REAL time to PAR completion: 4 mins 9 secs
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Total CPU time to PAR completion: 4 mins 32 secs
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Total CPU time to PAR completion: 4 mins 2 secs
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Peak Memory Usage: 265 MB
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Peak Memory Usage: 282 MB
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Placement: Completed - No errors found.
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Placement: Completed - No errors found.
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Routing: Completed - No errors found.
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Routing: Completed - No errors found.
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Number of error messages: 0
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Number of error messages: 0
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