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Release 8.2.02i - xst I.33
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Release 8.2.02i - xst I.33
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to ./xst/projnav.tmp
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--> Parameter TMPDIR set to ./xst/projnav.tmp
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CPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s
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CPU : 0.00 / 0.19 s | Elapsed : 0.00 / 0.00 s
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-->
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-->
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=========================================================================
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=========================================================================
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* HDL Compilation *
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* HDL Compilation *
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=========================================================================
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=========================================================================
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Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/common.vhd" in Library work.
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Architecture common of Entity common is up to date.
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Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/vga.vhd" in Library work.
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Architecture vga_arch of Entity vga is up to date.
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Architecture sync_arch of Entity sync is up to date.
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Compiling verilog file "vgachr.v" in library work
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Module compiled
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Module compiled
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Compiling verilog file "cpu8080.v" in library work
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Compiling verilog file "cpu8080.v" in library work
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Module compiled
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Module compiled
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Module compiled
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Compiling verilog file "testbench.v" in library work
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Compiling verilog file "testbench.v" in library work
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Module compiled
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Module compiled
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Module compiled
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Module compiled
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Module
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Module
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Line 28... |
Module compiled
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Module compiled
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Module compiled
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Module compiled
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No errors in compilation
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No errors in compilation
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Analysis of file <"testbench.prj"> succeeded.
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Analysis of file <"testbench.prj"> succeeded.
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CPU : 0.16 / 0.37 s | Elapsed : 0.00 / 0.00 s
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CPU : 0.56 / 0.75 s | Elapsed : 0.00 / 0.00 s
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-->
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-->
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Total memory usage is 107620 kilobytes
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Total memory usage is 112740 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 0 ( 0 filtered)
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Number of warnings : 0 ( 0 filtered)
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Number of infos : 0 ( 0 filtered)
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Number of infos : 0 ( 0 filtered)
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