Line 1... Line 1...
Release 8.2.02i - xst I.33Release 8.2.02i - xst I.33
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.20 s | Elapsed : 0.00 / 0.00 sCPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set to ./xst--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.20 s | Elapsed : 0.00 / 0.00 sCPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s
--> Reading design: testbench.prj--> Reading design: testbench.prj
TABLE OF CONTENTSTABLE OF CONTENTS
1) Synthesis Options Summary 1) Synthesis Options Summary
Line 33... Line 33...
Ignore Synthesis Constraint File : NOIgnore Synthesis Constraint File : NO
---- Target Parameters---- Target Parameters
Output File Name : "testbench"Output File Name : "testbench"
Output Format : NGCOutput Format : NGC
Target Device : xc3s200-5-pq208Target Device : xc3s1000-4-ft256
---- Source Options---- Source Options
Top Module Name : testbenchTop Module Name : testbench
Automatic FSM Extraction : YESAutomatic FSM Extraction : YES
FSM Encoding Algorithm : AutoFSM Encoding Algorithm : Auto
Line 94... Line 94...
==================================================================================================================================================
* HDL Compilation ** HDL Compilation *
==================================================================================================================================================
Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/common.vhd" in Library work.
Architecture common of Entity common is up to date.
Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/vga.vhd" in Library work.
Architecture vga_arch of Entity vga is up to date.
Architecture sync_arch of Entity sync is up to date.
Compiling verilog file "vgachr.v" in library work
Module compiled
Module compiled
Compiling verilog file "cpu8080.v" in library workCompiling verilog file "cpu8080.v" in library work
Module compiled
Module compiled Module compiled
Compiling verilog file "testbench.v" in library workCompiling verilog file "testbench.v" in library work
Module compiled Module compiled
Module compiled Module compiled
Module compiled Module compiled
Line 124... Line 133...
Analyzing hierarchy for module in library . Analyzing hierarchy for module in library .
Analyzing hierarchy for module in library . Analyzing hierarchy for module in library .
Analyzing hierarchy for module in library .
Analyzing hierarchy for module in library . Analyzing hierarchy for module in library .
Analyzing hierarchy for module in library . Analyzing hierarchy for module in library .
Analyzing hierarchy for module in library .
Analyzing hierarchy for entity in library (architecture ) with generics.
CLK_DIV = 4
FIT_TO_SCREEN = true
FREQ = 100000
LINES_PER_FRAME = 480
NUM_RGB_BITS = 3
PIXEL_WIDTH = 1
PIXELS_PER_LINE = 640
Analyzing hierarchy for module in library .
Analyzing hierarchy for entity in library (architecture ) with generics.
FREQ = 25000
PERIOD = 32
START = 26
VISIBLE = 640
WIDTH = 4
Analyzing hierarchy for entity in library (architecture ) with generics.
FREQ = 31
PERIOD = 16784
START = 15700
VISIBLE = 480
WIDTH = 64
Building hierarchy successfully finished.Building hierarchy successfully finished.
==================================================================================================================================================
* HDL Analysis ** HDL Analysis *
==================================================================================================================================================
Line 157... Line 195...
Module is correct for synthesis. Module is correct for synthesis.
Analyzing module in library . Analyzing module in library .
Module is correct for synthesis. Module is correct for synthesis.
Analyzing module in library .
Module is correct for synthesis.
Analyzing module in library .
Module is correct for synthesis.
Analyzing generic Entity in library (Architecture ).
PIXELS_PER_LINE = 640
CLK_DIV = 4
FIT_TO_SCREEN = true
FREQ = 100000
LINES_PER_FRAME = 480
NUM_RGB_BITS = 3
PIXEL_WIDTH = 1
Entity analyzed. Unit generated.
Analyzing generic Entity in library (Architecture ).
PERIOD = 32
WIDTH = 4
START = 26
VISIBLE = 640
FREQ = 25000
Entity analyzed. Unit generated.
Analyzing generic Entity in library (Architecture ).
FREQ = 31
PERIOD = 16784
START = 15700
VISIBLE = 480
WIDTH = 64
Entity analyzed. Unit generated.
Analyzing module in library .
Module is correct for synthesis.
==================================================================================================================================================
* HDL Synthesis ** HDL Synthesis *
==================================================================================================================================================
Performing bidirectional port resolution...Performing bidirectional port resolution...
INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic.
Synthesizing Unit . Synthesizing Unit .
Related source file is "testbench.v". Related source file is "testbench.v".
Found 512x8-bit ROM for signal <$mux0000>. Found 128x8-bit ROM for signal <$mux0000>.
Found 8-bit tristate buffer for signal . Found 8-bit tristate buffer for signal .
Summary: Summary:
inferred 1 ROM(s). inferred 1 ROM(s).
inferred 8 Tristate(s). inferred 8 Tristate(s).
Unit synthesized. Unit synthesized.
Line 245... Line 318...
WARNING:Xst:647 - Input > is never used. WARNING:Xst:647 - Input > is never used.
WARNING:Xst:737 - Found 6-bit latch for signal . WARNING:Xst:737 - Found 6-bit latch for signal .
WARNING:Xst:737 - Found 8-bit latch for signal . WARNING:Xst:737 - Found 8-bit latch for signal .
WARNING:Xst:737 - Found 8-bit latch for signal . WARNING:Xst:737 - Found 8-bit latch for signal .
Found 8-bit tristate buffer for signal . Found 8-bit tristate buffer for signal .
Found 6-bit comparator equal for signal <$cmp_eq0000> created at line 264. Found 6-bit comparator equal for signal <$cmp_eq0000> created at line 301.
Summary: Summary:
inferred 1 Comparator(s). inferred 1 Comparator(s).
inferred 8 Tristate(s). inferred 8 Tristate(s).
Unit synthesized. Unit synthesized.
Line 257... Line 330...
Synthesizing Unit . Synthesizing Unit .
Related source file is "cpu8080.v". Related source file is "cpu8080.v".
WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used.
Found 1-bit 8-to-1 multiplexer for signal . Found 1-bit 8-to-1 multiplexer for signal .
Found 1-bit 8-to-1 multiplexer for signal . Found 1-bit 8-to-1 multiplexer for signal .
Found 5-bit adder for signal <$add0001> created at line 1476. Found 5-bit adder for signal <$add0001> created at line 1484.
Found 8-bit adder carry out for signal <$addsub0000> created at line 1469. Found 8-bit adder carry out for signal <$addsub0000> created at line 1477.
Found 4-bit adder carry out for signal <$addsub0001> created at line 1470. Found 4-bit adder carry out for signal <$addsub0001> created at line 1478.
Found 6-bit subtractor for signal <$sub0000> created at line 1482. Found 6-bit subtractor for signal <$sub0000> created at line 1490.
Found 6-bit subtractor for signal <$sub0001> created at line 1488. Found 6-bit subtractor for signal <$sub0001> created at line 1496.
Found 9-bit subtractor for signal <$sub0002> created at line 1481. Found 9-bit subtractor for signal <$sub0002> created at line 1489.
Found 8-bit xor2 for signal <$xor0000> created at line 1499. Found 8-bit xor2 for signal <$xor0000> created at line 1507.
Found 1-bit xor8 for signal <$xor0002>. Found 1-bit xor8 for signal <$xor0002>.
Summary: Summary:
inferred 8 Adder/Subtractor(s). inferred 8 Adder/Subtractor(s).
inferred 10 Multiplexer(s). inferred 10 Multiplexer(s).
inferred 1 Xor(s). inferred 1 Xor(s).
Unit synthesized. Unit synthesized.
Synthesizing Unit .
Related source file is "vgachr.v".
Found 2048x8-bit ROM for signal .
Summary:
inferred 1 ROM(s).
Unit synthesized.
Synthesizing Unit .
Related source file is "C:/Xilinx/ISEexamples/cpu8080/vga.vhd".
Found 16-bit adder for signal <$addsub0000> created at line 396.
Found 1-bit register for signal .
Found 16-bit register for signal .
Found 1-bit register for signal .
Found 1-bit register for signal .
Summary:
inferred 19 D-type flip-flop(s).
inferred 1 Adder/Subtractor(s).
Unit synthesized.
Synthesizing Unit .
Related source file is "C:/Xilinx/ISEexamples/cpu8080/vga.vhd".
Found 16-bit adder for signal <$addsub0000> created at line 396.
Found 1-bit register for signal .
Found 16-bit register for signal .
Found 1-bit register for signal .
Found 1-bit register for signal .
Summary:
inferred 19 D-type flip-flop(s).
inferred 1 Adder/Subtractor(s).
Unit synthesized.
Synthesizing Unit . Synthesizing Unit .
Related source file is "testbench.v". Related source file is "testbench.v".
Found 1-bit register for signal . Found 1-bit register for signal .
Found 8-bit tristate buffer for signal . Found 8-bit tristate buffer for signal .
Found 8-bit register for signal . Found 8-bit register for signal .
Line 290... Line 397...
Synthesizing Unit . Synthesizing Unit .
Related source file is "cpu8080.v". Related source file is "cpu8080.v".
Found finite state machine for signal . Found finite state machine for signal .
----------------------------------------------------------------------- -----------------------------------------------------------------------
| States | 30 | | States | 31 |
| Transitions | 899 | | Transitions | 900 |
| Inputs | 140 | | Inputs | 140 |
| Outputs | 31 | | Outputs | 33 |
| Clock | clock (rising_edge) | | Clock | clock (rising_edge) |
| Reset | reset (positive) | | Reset | reset (positive) |
| Reset type | synchronous | | Reset type | synchronous |
| Reset State | 00001 | | Reset State | 00001 |
| Encoding | automatic | | Encoding | automatic |
| Implementation | LUT | | Implementation | LUT |
----------------------------------------------------------------------- -----------------------------------------------------------------------
Found 4x1-bit ROM for signal <$mux0042> created at line 293. Found 4x1-bit ROM for signal <$mux0043> created at line 301.
Found 16-bit register for signal . Found 16-bit register for signal .
Found 1-bit register for signal . Found 1-bit register for signal .
Found 1-bit register for signal . Found 1-bit register for signal .
Found 1-bit register for signal . Found 1-bit register for signal .
Found 1-bit register for signal . Found 1-bit register for signal .
Found 1-bit register for signal . Found 1-bit register for signal .
Found 8-bit tristate buffer for signal . Found 8-bit tristate buffer for signal .
Found 32-bit adder for signal <$add0001> created at line 475. Found 32-bit adder for signal <$add0001> created at line 483.
Found 32-bit adder for signal <$add0002> created at line 487. Found 32-bit adder for signal <$add0002> created at line 495.
Found 32-bit adder for signal <$add0003> created at line 499. Found 32-bit adder for signal <$add0003> created at line 507.
Found 16-bit adder for signal <$add0004> created at line 959. Found 16-bit adder for signal <$add0004> created at line 967.
Found 16-bit adder for signal <$add0005> created at line 870. Found 16-bit adder for signal <$add0005> created at line 878.
Found 32-bit adder for signal <$add0006> created at line 544. Found 32-bit adder for signal <$add0006> created at line 552.
Found 32-bit adder for signal <$add0007> created at line 532. Found 32-bit adder for signal <$add0007> created at line 540.
Found 32-bit adder for signal <$add0008> created at line 520. Found 32-bit adder for signal <$add0008> created at line 528.
Found 17-bit adder for signal <$add0009> created at line 465. Found 17-bit adder for signal <$add0009> created at line 473.
Found 17-bit adder for signal <$addsub0000>. Found 17-bit adder for signal <$addsub0000>.
Found 17-bit adder for signal <$addsub0001>. Found 17-bit adder for signal <$addsub0001>.
Found 17-bit adder for signal <$addsub0002>. Found 17-bit adder for signal <$addsub0002>.
Found 8-bit adder for signal <$addsub0003>. Found 8-bit adder for signal <$addsub0003>.
Found 8-bit addsub for signal <$addsub0004>. Found 8-bit addsub for signal <$addsub0004>.
Found 8-bit addsub for signal <$addsub0005>. Found 8-bit addsub for signal <$addsub0005>.
Found 8-bit addsub for signal <$addsub0006>. Found 8-bit addsub for signal <$addsub0006>.
Found 16-bit adder for signal <$addsub0007> created at line 1030. Found 16-bit adder for signal <$addsub0007> created at line 1038.
Found 16-bit adder for signal <$addsub0008> created at line 1071. Found 16-bit adder for signal <$addsub0008> created at line 1079.
Found 8-bit adder carry out for signal <$addsub0009>. Found 8-bit adder carry out for signal <$addsub0009>.
Found 4-bit adder carry out for signal <$addsub0010> created at line 340. Found 4-bit adder carry out for signal <$addsub0010> created at line 348.
Found 8-bit adder carry out for signal <$addsub0011>. Found 8-bit adder carry out for signal <$addsub0011>.
Found 4-bit comparator greater for signal <$cmp_gt0000> created at line 337. Found 4-bit comparator greater for signal <$cmp_gt0000> created at line 345.
Found 4-bit comparator greater for signal <$cmp_gt0001> created at line 1286. Found 4-bit comparator greater for signal <$cmp_gt0001> created at line 1294.
Found 3-bit 4-to-1 multiplexer for signal <$mux0021> created at line 293. Found 3-bit 4-to-1 multiplexer for signal <$mux0022> created at line 301.
Found 8-bit 4-to-1 multiplexer for signal <$mux0022> created at line 293. Found 8-bit 4-to-1 multiplexer for signal <$mux0023> created at line 301.
Found 3-bit 4-to-1 multiplexer for signal <$mux0024> created at line 293. Found 3-bit 4-to-1 multiplexer for signal <$mux0025> created at line 301.
Found 8-bit 4-to-1 multiplexer for signal <$mux0030> created at line 293. Found 8-bit 4-to-1 multiplexer for signal <$mux0031> created at line 301.
Found 3-bit 4-to-1 multiplexer for signal <$mux0044>. Found 3-bit 4-to-1 multiplexer for signal <$mux0045>.
Found 3-bit 4-to-1 multiplexer for signal <$mux0049> created at line 297. Found 3-bit 4-to-1 multiplexer for signal <$mux0050> created at line 305.
Found 8-bit 4-to-1 multiplexer for signal <$mux0050>. Found 8-bit 4-to-1 multiplexer for signal <$mux0051>.
Found 16-bit adder for signal <$share0000> created at line 293. Found 16-bit adder for signal <$share0000> created at line 301.
Found 6-bit adder for signal <$share0005> created at line 260. Found 6-bit adder for signal <$share0005> created at line 262.
Found 16-bit addsub for signal <$share0006> created at line 293. Found 16-bit addsub for signal <$share0006> created at line 301.
Found 32-bit subtractor for signal <$sub0000> created at line 520. Found 32-bit subtractor for signal <$sub0000> created at line 528.
Found 32-bit subtractor for signal <$sub0001> created at line 532. Found 32-bit subtractor for signal <$sub0001> created at line 540.
Found 32-bit subtractor for signal <$sub0002> created at line 544. Found 32-bit subtractor for signal <$sub0002> created at line 552.
Found 16-bit subtractor for signal <$sub0003> created at line 741. Found 16-bit subtractor for signal <$sub0003> created at line 749.
Found 1-bit register for signal . Found 1-bit register for signal .
Found 8-bit register for signal . Found 8-bit register for signal .
Found 8-bit register for signal . Found 8-bit register for signal .
Found 3-bit register for signal . Found 3-bit register for signal .
Found 1-bit register for signal . Found 1-bit register for signal .
Found 1-bit register for signal . Found 1-bit register for signal .
Found 1-bit register for signal . Found 1-bit register for signal .
Found 8-bit register for signal . Found 8-bit register for signal .
Found 1-bit register for signal . Found 1-bit register for signal .
Found 1-bit register for signal .
Found 1-bit register for signal . Found 1-bit register for signal .
Found 8-bit register for signal .
Found 1-bit register for signal . Found 1-bit register for signal .
Found 16-bit register for signal . Found 16-bit register for signal .
Found 2-bit register for signal . Found 2-bit register for signal .
Found 16-bit register for signal . Found 16-bit register for signal .
Found 8-bit register for signal . Found 8-bit register for signal .
Line 374... Line 483...
Found 8-bit register for signal . Found 8-bit register for signal .
Found 1-bit register for signal . Found 1-bit register for signal .
Summary: Summary:
inferred 1 Finite State Machine(s). inferred 1 Finite State Machine(s).
inferred 1 ROM(s). inferred 1 ROM(s).
inferred 228 D-type flip-flop(s). inferred 237 D-type flip-flop(s).
inferred 34 Adder/Subtractor(s). inferred 34 Adder/Subtractor(s).
inferred 2 Comparator(s). inferred 2 Comparator(s).
inferred 52 Multiplexer(s). inferred 52 Multiplexer(s).
inferred 8 Tristate(s). inferred 8 Tristate(s).
Unit synthesized. Unit synthesized.
Synthesizing Unit . Synthesizing Unit .
Related source file is "testbench.v". Related source file is "C:/Xilinx/ISEexamples/cpu8080/vga.vhd".
WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used.
WARNING:Xst:646 - Signal > is assigned but never used.
Found 3-bit register for signal .
Found 1-bit register for signal .
Found 8-bit up counter for signal .
Found 1-bit register for signal .
Found 3-bit register for signal .
Found 16-bit register for signal .
Found 1-bit register for signal .
Found 9-bit register for signal .
Summary:
inferred 1 Counter(s).
inferred 34 D-type flip-flop(s).
Unit synthesized.
Synthesizing Unit .
Related source file is "vgachr.v".
WARNING:Xst:646 - Signal is assigned but never used.
Found 1920x8-bit single-port block RAM for signal .
-----------------------------------------------------------------------
| ram_style | Auto | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 1920-word x 8-bit | |
| mode | read-first | |
| clkA | connected to signal | rise |
| weA | connected to signal | high |
| addrA | connected to signal | |
| diA | connected to signal | |
| doA | connected to signal | |
-----------------------------------------------------------------------
Found 1920x8-bit dual-port distributed RAM for signal .
-----------------------------------------------------------------------
| ram_style | Auto | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 1920-word x 8-bit | |
| clkA | connected to signal | rise |
| weA | connected to signal | high |
| addrA | connected to signal | |
| diA | connected to signal | |
-----------------------------------------------------------------------
| Port B |
| aspect ratio | 1920-word x 8-bit | |
| addrB | connected to internal node | |
| doB | connected to internal node | |
-----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
INFO:Xst:2117 - HDL ADVISOR - Mux Selector of Case statement line 320 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
- add an 'INIT' attribute on signal (optimization is then done without any risk)
- use the attribute 'signal_encoding user' to avoid onehot optimization
- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
Found finite state machine for signal .
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 4 |
| Inputs | 0 |
| Outputs | 6 |
| Clock | clk (rising_edge) |
| Clock enable | $or0000 (positive) |
| Reset | $or0001 (positive) |
| Reset type | synchronous |
| Reset State | 00 |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
WARNING:Xst:643 - "vgachr.v" line 361: The result of a 9x6-bit multiplication is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
Found 8-bit tristate buffer for signal . Found 8-bit tristate buffer for signal .
Found 9-bit subtractor for signal <$addsub0000> created at line 361.
Found 11-bit adder for signal <$addsub0001> created at line 361.
Found 7-bit comparator greatequal for signal <$cmp_ge0000> created at line 301.
Found 5-bit comparator greatequal for signal <$cmp_ge0001> created at line 305.
Found 7-bit comparator less for signal <$cmp_lt0000> created at line 301.
Found 5-bit comparator less for signal <$cmp_lt0001> created at line 305.
Found 8-bit comparator less for signal <$cmp_lt0002> created at line 361.
Found 9x6-bit multiplier for signal <$mult0002> created at line 361.
Found 7-bit up counter for signal .
Found 5-bit up counter for signal .
Found 16-bit register for signal .
Found 5-bit up counter for signal .
Found 11-bit up accumulator for signal .
Summary: Summary:
inferred 1 Finite State Machine(s).
inferred 2 RAM(s).
inferred 3 Counter(s).
inferred 1 Accumulator(s).
inferred 16 D-type flip-flop(s).
inferred 3 Adder/Subtractor(s).
inferred 1 Multiplier(s).
inferred 5 Comparator(s).
inferred 8 Tristate(s). inferred 8 Tristate(s).
Unit synthesized.
Synthesizing Unit .
Related source file is "vgachr.v".
Found finite state machine for signal .
-----------------------------------------------------------------------
| States | 7 |
| Transitions | 12 |
| Inputs | 5 |
| Outputs | 7 |
| Clock | clock (falling_edge) |
| Clock enable | $or0000 (negative) |
| Reset | reset (positive) |
| Reset type | synchronous |
| Reset State | 000011 |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 8-bit tristate buffer for signal .
Found 11-bit adder for signal <$addsub0000> created at line 175.
Found 11-bit adder for signal <$addsub0001> created at line 208.
Found 8-bit comparator greatequal for signal <$cmp_ge0000> created at line 143.
Found 11-bit comparator less for signal <$cmp_lt0000> created at line 206.
Found 8-bit register for signal .
Found 11-bit register for signal .
Found 8-bit tristate buffer for signal .
Found 1-bit register for signal .
Found 8-bit register for signal .
Found 1-bit register for signal .
Found 11-bit register for signal .
Found 8-bit register for signal .
Found 1-bit register for signal .
Found 1-bit register for signal .
Summary:
inferred 1 Finite State Machine(s).
inferred 50 D-type flip-flop(s).
inferred 2 Adder/Subtractor(s).
inferred 2 Comparator(s).
inferred 16 Tristate(s).
Unit synthesized.
Synthesizing Unit .
Related source file is "testbench.v".
Found 8-bit up counter for signal .
Summary:
inferred 1 Counter(s).
Unit synthesized. Unit synthesized.
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
==================================================================================================================================================
HDL Synthesis ReportHDL Synthesis Report
Macro StatisticsMacro Statistics
# RAMs : 1# RAMs : 2
1024x8-bit single-port block RAM : 1 1024x8-bit single-port block RAM : 1
# ROMs : 2 1920x8-bit dual-port distributed RAM : 1
# ROMs : 3
128x8-bit ROM : 1
2048x8-bit ROM : 1
4x1-bit ROM : 1 4x1-bit ROM : 1
512x8-bit ROM : 1# Multipliers : 1
# Adders/Subtractors : 42 9x6-bit multiplier : 1
16-bit adder : 5# Adders/Subtractors : 49
11-bit adder : 4
16-bit adder : 7
16-bit addsub : 1 16-bit addsub : 1
16-bit subtractor : 1 16-bit subtractor : 1
17-bit adder : 8 17-bit adder : 8
32-bit adder : 6 32-bit adder : 6
32-bit subtractor : 3 32-bit subtractor : 3
Line 416... Line 666...
6-bit subtractor : 2 6-bit subtractor : 2
8-bit adder : 1 8-bit adder : 1
8-bit adder carry out : 3 8-bit adder carry out : 3
8-bit addsub : 3 8-bit addsub : 3
9-bit adder : 3 9-bit adder : 3
9-bit subtractor : 2 9-bit subtractor : 3
# Registers : 54# Counters : 5
1-bit register : 23 5-bit up counter : 2
16-bit register : 5 7-bit up counter : 1
8-bit up counter : 2
# Accumulators : 1
11-bit up accumulator : 1
# Registers : 81
1-bit register : 37
11-bit register : 2
16-bit register : 9
2-bit register : 1 2-bit register : 1
3-bit register : 2 3-bit register : 4
4-bit register : 1 4-bit register : 1
6-bit register : 1 6-bit register : 1
8-bit register : 21 8-bit register : 25
9-bit register : 1
# Latches : 12# Latches : 12
6-bit latch : 4 6-bit latch : 4
8-bit latch : 8 8-bit latch : 8
# Comparators : 7# Comparators : 14
11-bit comparator less : 1
4-bit comparator equal : 1 4-bit comparator equal : 1
4-bit comparator greater : 2 4-bit comparator greater : 2
5-bit comparator greatequal : 1
5-bit comparator less : 1
6-bit comparator equal : 4 6-bit comparator equal : 4
7-bit comparator greatequal : 1
7-bit comparator less : 1
8-bit comparator greatequal : 1
8-bit comparator less : 1
# Multiplexers : 20# Multiplexers : 20
1-bit 4-to-1 multiplexer : 8 1-bit 4-to-1 multiplexer : 8
1-bit 8-to-1 multiplexer : 2 1-bit 8-to-1 multiplexer : 2
3-bit 4-to-1 multiplexer : 4 3-bit 4-to-1 multiplexer : 4
8-bit 4-to-1 multiplexer : 3 8-bit 4-to-1 multiplexer : 3
8-bit 8-to-1 multiplexer : 3 8-bit 8-to-1 multiplexer : 3
# Tristates : 10# Tristates : 19
8-bit tristate buffer : 10 1-bit tristate buffer : 8
8-bit tristate buffer : 11
# Xors : 2# Xors : 2
1-bit xor8 : 1 1-bit xor8 : 1
8-bit xor2 : 1 8-bit xor2 : 1
==================================================================================================================================================
==================================================================================================================================================
* Advanced HDL Synthesis ** Advanced HDL Synthesis *
==================================================================================================================================================
Analyzing FSM for best encoding.
Optimizing FSM on signal with sequential encoding.
--------------------
State | Encoding
--------------------
000000 | 010
000001 | 001
000010 | 011
000011 | 000
000100 | 100
000101 | 101
000110 | 110
--------------------
Analyzing FSM for best encoding.
Optimizing FSM on signal with gray encoding.
-------------------
State | Encoding
-------------------
00 | 00
01 | 01
10 | 11
11 | 10
-------------------
Analyzing FSM for best encoding. Analyzing FSM for best encoding.
Optimizing FSM on signal with speed1 encoding. Optimizing FSM on signal with speed1 encoding.
---------------------------------------------------------------------------------------
State | Encoding State | Encoding
---------------------------------------------------------------------------------------
00001 | 10000000000000000000000000000000 00001 | 010000000000000000000000000000000
00010 | 01000000000000000000000000000000 00010 | 001000000000000000000000000000000
00011 | 00000010000000000000000000000000 00011 | 000100000000000000000000000000000
00100 | 00000001001000000000000000000000 00100 | 000000001000000000000000000000000
00101 | 00010000001000000000000000000000 00101 | 000000000100000000000000000000001
00110 | 00000000001001000000000000000000 00110 | 000001000000000000000000000000001
00111 | 00000000001000100000000000000000 00111 | 000000000000001000000000000000001
01000 | 00000000001000010000000000000000 01000 | 000000000000000100000000000000001
01001 | 00000000001000001000000000000000 01001 | 000000000000000001000000000000001
01010 | 00000000000000000000000010000001 01010 | 000000000000000000100000000000001
01011 | 00000000001000000000010000000000 01011 | 100000000000000010000000000000000
01100 | 00001000000000000000000000000000 01100 | 000000000000000000000001000000001
01101 | 00000000100000000000000000000000 01101 | 000000100000000000000000000000000
01110 | 00000000010000000000000000000000 01110 | 000000000010000000000000000000000
01111 | 00000000000100000000000000000001 01111 | 000000000001000000000000000000000
10000 | 00000100000000000000000000000000 10000 | 100000000000100000000000000000000
10001 | 00000000000000000000000000100000 10001 | 000000010000000000000000000000000
10010 | 00000000001000000100000000000000 10010 | 000000000000000000000000000010000
10011 | 00000000000000000000000100000000 10011 | 000000000000000000010000000000001
10100 | 00000000001000000000000000010000 10100 | 000000000000000000000000010000000
10101 | 00000000000000000000000001000000 10101 | 000000000000000000000000000001001
10110 | 00000000000000000000000000001000 10110 | 000000000000000000000000000100000
10111 | 00000000000000000000000000000100 10111 | 000000000000000000000000000000100
11000 | 00000000001000000000000000000010 11000 | 000000000000000000000000000000010
11001 | 00000000000010000000000000000001 11001 | 000000000000000000000000001000001
11010 | 00000000000000000010000000000001 11010 | 100000000000010000000000000000000
11011 | 00000000000000000000100000000001 11011 | 100000000000000000001000000000000
11100 | 00000000000000000000001000000001 11100 | 100000000000000000000010000000000
11101 | 00000000000000000001000000000000 11101 | 100000000000000000000000100000000
11110 | 00100000001000000000000000000000 11110 | 000000000000000000000100000000000
------------------------------------------- 11111 | 000010000000000000000000000000001
--------------------------------------------
Analyzing FSM for best encoding. Analyzing FSM for best encoding.
Optimizing FSM on signal with gray encoding. Optimizing FSM on signal with gray encoding.
--------------------------------------
State | Encoding State | Encoding
--------------------------------------
0000 | 00 0000 | 00
0001 | 01 0001 | 01
0010 | 11 0010 | 11
--------------------------------------
Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx.Loading device for application Rf_Device from file '3s1000.nph' in environment C:\Xilinx.
WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block .
INFO:Xst:1651 - Address input of ROM is tied to register . INFO:Xst:1651 - Address input of ROM is tied to register .
INFO:Xst:1650 - The register is removed and the ROM is implemented as read-only block RAM.INFO:Xst:1650 - The register is removed and the ROM is implemented as read-only block RAM.
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 8 FFs/Latches, which will be removed :
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
==================================================================================================================================================
Advanced HDL Synthesis ReportAdvanced HDL Synthesis Report
Macro StatisticsMacro Statistics
# FSMs : 2# FSMs : 4
# RAMs : 2# RAMs : 3
1024x8-bit single-port block RAM : 1 1024x8-bit single-port block RAM : 1
512x8-bit single-port block RAM : 1 128x8-bit single-port block RAM : 1
# ROMs : 1 1920x8-bit dual-port distributed RAM : 1
# ROMs : 2
2048x8-bit ROM : 1
4x1-bit ROM : 1 4x1-bit ROM : 1
# Adders/Subtractors : 42# Multipliers : 1
16-bit adder : 5 9x6-bit multiplier : 1
# Adders/Subtractors : 49
11-bit adder : 4
16-bit adder : 7
16-bit addsub : 1 16-bit addsub : 1
16-bit subtractor : 1 16-bit subtractor : 1
17-bit adder : 8 17-bit adder : 8
32-bit adder : 6 32-bit adder : 6
32-bit subtractor : 3 32-bit subtractor : 3
Line 528... Line 834...
6-bit subtractor : 2 6-bit subtractor : 2
8-bit adder : 1 8-bit adder : 1
8-bit adder carry out : 3 8-bit adder carry out : 3
8-bit addsub : 3 8-bit addsub : 3
9-bit adder : 3 9-bit adder : 3
9-bit subtractor : 2 9-bit subtractor : 3
# Registers : 319# Counters : 5
Flip-Flops : 319 5-bit up counter : 2
7-bit up counter : 1
8-bit up counter : 2
# Accumulators : 1
11-bit up accumulator : 1
# Registers : 455
Flip-Flops : 455
# Latches : 12# Latches : 12
6-bit latch : 4 6-bit latch : 4
8-bit latch : 8 8-bit latch : 8
# Comparators : 7# Comparators : 14
11-bit comparator less : 1
4-bit comparator equal : 1 4-bit comparator equal : 1
4-bit comparator greater : 2 4-bit comparator greater : 2
5-bit comparator greatequal : 1
5-bit comparator less : 1
6-bit comparator equal : 4 6-bit comparator equal : 4
7-bit comparator greatequal : 1
7-bit comparator less : 1
8-bit comparator greatequal : 1
8-bit comparator less : 1
# Multiplexers : 20# Multiplexers : 20
1-bit 4-to-1 multiplexer : 8 1-bit 4-to-1 multiplexer : 8
1-bit 8-to-1 multiplexer : 2 1-bit 8-to-1 multiplexer : 2
3-bit 4-to-1 multiplexer : 4 3-bit 4-to-1 multiplexer : 4
8-bit 4-to-1 multiplexer : 3 8-bit 4-to-1 multiplexer : 3
Line 553... Line 872...
==================================================================================================================================================
==================================================================================================================================================
* Low Level Synthesis ** Low Level Synthesis *
==================================================================================================================================================
WARNING:Xst:2040 - Unit testbench: 8 multi-source signals are replaced by logic (pull-up yes): N185, N187, N189, N1911, N193, N195, N197, N199.WARNING:Xst:1988 - Unit : instances , of unit and unit are dual, second instance is removed
WARNING:Xst:1988 - Unit : instances , of unit and unit are dual, second instance is removed
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:2040 - Unit testbench: 16 multi-source signals are replaced by logic (pull-up yes): adm3a/cmdata<0>, adm3a/cmdata<1>, adm3a/cmdata<2>, adm3a/cmdata<3>, adm3a/cmdata<4>, adm3a/cmdata<5>, adm3a/cmdata<6>, adm3a/cmdata<7>, N187, N189, N1911, N193, N195, N197, N199, N2011.
WARNING:Xst:2042 - Unit chrmemmap: 8 internal tristates are replaced by logic (pull-up yes): data<0>, data<1>, data<2>, data<3>, data<4>, data<5>, data<6>, data<7>.
Optimizing unit ... Optimizing unit ...
Optimizing unit ...
Optimizing unit ...
Optimizing unit ...
Optimizing unit ... Optimizing unit ...
Mapping all equations...Mapping all equations...
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
Building and optimizing final netlist ...Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block testbench, actual ratio is 69.Found area constraint ratio of 100 (+ 5) on block testbench, actual ratio is 28.
FlipFlop cpu/addr_0 has been replicated 2 time(s)FlipFlop adm3a/cmaddr_0 has been replicated 5 time(s)
FlipFlop cpu/addr_1 has been replicated 2 time(s)FlipFlop adm3a/cmaddr_1 has been replicated 5 time(s)
FlipFlop cpu/addr_2 has been replicated 2 time(s)FlipFlop adm3a/cmaddr_2 has been replicated 5 time(s)
FlipFlop adm3a/cmaddr_3 has been replicated 5 time(s)
FlipFlop adm3a/display/chrcnt_0 has been replicated 76 time(s)
FlipFlop adm3a/display/chrcnt_1 has been replicated 76 time(s)
FlipFlop adm3a/display/chrcnt_2 has been replicated 76 time(s)
FlipFlop adm3a/display/chrcnt_3 has been replicated 76 time(s)
FlipFlop adm3a/display/chrcnt_4 has been replicated 2 time(s)
FlipFlop adm3a/display/scnadr_4 has been replicated 3 time(s)
FlipFlop cpu/addr_2 has been replicated 1 time(s)
FlipFlop cpu/addr_3 has been replicated 1 time(s)FlipFlop cpu/addr_3 has been replicated 1 time(s)
FlipFlop cpu/readio has been replicated 1 time(s)
Final Macro Processing ...Final Macro Processing ...
Processing Unit :
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:2387 - HDL ADVISOR - A 3-bit shift register was found for signal and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
Unit processed.
==================================================================================================================================================
Final Register ReportFinal Register Report
Macro StatisticsMacro Statistics
# Registers : 326# Registers : 811
Flip-Flops : 326 Flip-Flops : 811
==================================================================================================================================================
==================================================================================================================================================
* Partition Report ** Partition Report *
Line 601... Line 1080...
Output Format : NGCOutput Format : NGC
Optimization Goal : SpeedOptimization Goal : Speed
Keep Hierarchy : NOKeep Hierarchy : NO
Design StatisticsDesign Statistics
# IOs : 33# IOs : 44
Cell Usage :Cell Usage :
# BELS : 3000# BELS : 5813
# GND : 1# GND : 1
# INV : 83# INV : 95
# LUT1 : 139# LUT1 : 189
# LUT2 : 152# LUT2 : 360
# LUT2_D : 1# LUT2_D : 9
# LUT2_L : 13# LUT2_L : 3
# LUT3 : 408# LUT3 : 1100
# LUT3_D : 9# LUT3_D : 7
# LUT3_L : 11# LUT3_L : 3
# LUT4 : 1358# LUT4 : 2221
# LUT4_D : 13# LUT4_D : 55
# LUT4_L : 66# LUT4_L : 41
# MULT_AND : 28# MULT_AND : 28
# MUXCY : 279# MUXCY : 575
# MUXF5 : 176# MUXF5 : 586
# MUXF6 : 24# MUXF6 : 167
# MUXF7 : 55
# MUXF8 : 23
# VCC : 1# VCC : 1
# XORCY : 238# XORCY : 294
# FlipFlops/Latches : 403# FlipFlops/Latches : 899
# FDE : 214# FD : 4
# FDE_1 : 8# FDC : 9
# FDR : 22# FDCE : 53
# FDRE : 5# FDE : 230
# FDRE_1 : 42# FDE_1 : 54
# FDRS : 29# FDP : 1
# FDRSE : 3# FDPE : 7
# FDR : 23
# FDRE : 335
# FDRE_1 : 60
# FDRS : 30
# FDRSE : 2
# FDS : 2# FDS : 2
# FDSE : 1# FDSE : 1
# LDCE : 53# LDCE : 56
# LDE_1 : 24# LDE_1 : 32
# RAMS : 2# RAMS : 842
# RAM16X1D : 840
# RAMB16_S9 : 2# RAMB16_S9 : 2
# Clock Buffers : 2# Clock Buffers : 3
# BUFG : 1
# BUFGP : 2# BUFGP : 2
# IO Buffers : 31# IO Buffers : 42
# IBUF : 1# IBUF : 1
# IOBUF : 8# IOBUF : 8
# OBUF : 22# OBUF : 33
# MULTs : 1
# MULT18X18 : 1
==================================================================================================================================================
Device utilization summary:Device utilization summary:
------------------------------------------------------
Selected Device : 3s200pq208-5Selected Device : 3s1000ft256-4
Number of Slices: 1196 out of 1920 62% Number of Slices: 2130 out of 7680 27%
Number of Slice Flip Flops: 403 out of 3840 10% Number of Slice Flip Flops: 899 out of 15360 5%
Number of 4 input LUTs: 2253 out of 3840 58% Number of 4 input LUTs: 5763 out of 15360 37%
Number of IOs: 33 Number used as logic: 4083
Number of bonded IOBs: 33 out of 141 23% Number used as RAMs: 1680
Number of BRAMs: 2 out of 12 16% Number of IOs: 44
Number of GCLKs: 2 out of 8 25% Number of bonded IOBs: 44 out of 173 25%
Number of BRAMs: 2 out of 24 8%
Number of MULT18X18s: 1 out of 24 4%
Number of GCLKs: 3 out of 8 37%
==================================================================================================================================================
TIMING REPORTTIMING REPORT
Line 671... Line 1164...
Clock Information:Clock Information:
------------------------------------
-----------------------------------------------------+--------------------------------+-------+-----------------------------------------------------+--------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------------------------+--------------------------------+-------+-----------------------------------------------------+--------------------------------+-------+
clock | BUFGP | 326 |clkdiv_31 | BUFG | 331 |
reset | BUFGP | 24 |clock | BUFGP | 1320 |
select1/selectd/_and0000(select1/selectd/_and00001:O)| NONE(*)(select1/selectd/mask_5)| 11 |reset_n | BUFGP | 32 |
select1/selectc/_and0000(select1/selectc/_and00001:O)| NONE(*)(select1/selectc/comp_0)| 14 |select1/selectd/_and0000(select1/selectd/_and00001:O)| NONE(*)(select1/selectd/comp_5)| 14 |
select1/selectb/_and0000(select1/selectb/_and00001:O)| NONE(*)(select1/selectb/mask_2)| 14 |select1/selectc/_and0000(select1/selectc/_and00001:O)| NONE(*)(select1/selectc/comp_3)| 14 |
select1/selecta/_and0000(select1/selecta/_and00001:O)| NONE(*)(select1/selecta/comp_4)| 14 |select1/selectb/_and0000(select1/selectb/_and00001:O)| NONE(*)(select1/selectb/comp_4)| 14 |
select1/selecta/_and0000(select1/selecta/_and00001:O)| NONE(*)(select1/selecta/mask_6)| 14 |
-----------------------------------------------------+--------------------------------+-------+-----------------------------------------------------+--------------------------------+-------+
(*) These 4 clock signal(s) are generated by combinatorial logic,(*) These 4 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information:Asynchronous Control Signals Information:
--------------------------------------------------------------------------------
-----------------------------------+------------------------+-------+-----------------------------------+----------------------------------------------------+-------+
Control Signal | Buffer(FF name) | Load |Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+-----------------------------------+----------------------------------------------------+-------+
reset | BUFGP | 53 |reset(reset1_INV_0:O) | NONE(adm3a/display/vgai/gen_syncs_fit.hsync/sync_r)| 126 |
-----------------------------------+------------------------+-------+-----------------------------------+----------------------------------------------------+-------+
Timing Summary:Timing Summary:
------------------------------
Speed Grade: -5Speed Grade: -4
Minimum period: 18.139ns (Maximum Frequency: 55.130MHz) Minimum period: 33.473ns (Maximum Frequency: 29.875MHz)
Minimum input arrival time before clock: 15.913ns Minimum input arrival time before clock: 10.291ns
Maximum output required time after clock: 18.039ns Maximum output required time after clock: 19.654ns
Maximum combinational path delay: No path found Maximum combinational path delay: No path found
Timing Detail:Timing Detail:
----------------------------
All values displayed in nanoseconds (ns)All values displayed in nanoseconds (ns)
==================================================================================================================================================
Timing constraint: Default period analysis for Clock 'clkdiv_31'
Clock period: 24.368ns (frequency: 41.037MHz)
Total number of paths / destination ports: 40013 / 419
-------------------------------------------------------------------------
Delay: 12.184ns (Levels of Logic = 7)
Source: cpu/addr_4 (FF)
Destination: intc/datai_6 (FF)
Source Clock: clkdiv_31 rising
Destination Clock: clkdiv_31 falling
Data Path: cpu/addr_4 to intc/datai_6
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDE:C->Q 8 0.720 1.278 cpu/addr_4 (cpu/addr_4)
LUT4:I1->O 1 0.551 0.000 select1/selectc/selectout791 (N14518)
MUXF5:I1->O 1 0.360 1.140 select1/selectc/selectout79_f5 (select1/selectc/selectout_map4980)
LUT4_D:I0->O 3 0.551 0.975 select1/selectc/selectout169 (select1/selectc/selectout_map5007)
LUT4:I2->O 25 0.551 2.008 intc/_not0027_SW0 (intc/_and0001)
LUT4_D:I1->O 6 0.551 1.198 intc/_mux0008<4>1 (N19)
LUT4:I1->O 1 0.551 0.996 intc/_mux0008<7>12 (intc/_mux0008<7>_map4950)
LUT4:I1->O 1 0.551 0.000 intc/_mux0008<7>33 (intc/_mux0008<7>)
FDE_1:D 0.203 intc/datai_7
----------------------------------------
Total 12.184ns (4.589ns logic, 7.595ns route)
(37.7% logic, 62.3% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'clock'Timing constraint: Default period analysis for Clock 'clock'
Clock period: 18.139ns (frequency: 55.130MHz) Clock period: 33.473ns (frequency: 29.875MHz)
Total number of paths / destination ports: 22435 / 411 Total number of paths / destination ports: 158202401 / 9605
--------------------------------------------------------------------------------------------------------------------------------------------------
Delay: 9.069ns (Levels of Logic = 6)Delay: 33.473ns (Levels of Logic = 26)
Source: cpu/addr_10 (FF) Source: adm3a/display/scnadr_4_1 (FF)
Destination: intc/active_7 (FF) Destination: adm3a/display/pixeldata_5 (FF)
Source Clock: clock rising Source Clock: clock rising
Destination Clock: clock falling Destination Clock: clock rising
Data Path: adm3a/display/scnadr_4_1 to adm3a/display/pixeldata_5
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRE:C->Q 2 0.720 1.216 adm3a/display/scnadr_4_1 (adm3a/display/scnadr_4_1)
LUT2:I0->O 1 0.551 0.000 adm3a/display/Madd__COND_40_lut<4>_1 (adm3a/display/Madd__COND_40_lut<4>)
MUXCY:S->O 1 0.500 0.000 adm3a/display/Madd__COND_40_cy<4> (adm3a/display/Madd__COND_40_cy<4>)
MUXCY:CI->O 1 0.064 0.000 adm3a/display/Madd__COND_40_cy<5> (adm3a/display/Madd__COND_40_cy<5>)
MUXCY:CI->O 1 0.064 0.000 adm3a/display/Madd__COND_40_cy<6> (adm3a/display/Madd__COND_40_cy<6>)
XORCY:CI->O 392 0.904 3.983 adm3a/display/Madd__COND_40_xor<7> (adm3a/display/_COND_40<7>)
LUT3:I2->O 1 0.551 0.000 adm3a/display/_COND_40<7>23 (adm3a/display/N251234567)
MUXF5:I0->O 1 0.360 0.000 adm3a/display/_COND_40<4>_f5_10 (adm3a/display/_COND_40<4>_f511)
MUXF6:I0->O 1 0.342 0.996 adm3a/display/_COND_40<5>_f6_4 (adm3a/display/_COND_40<5>_f65)
LUT3:I1->O 1 0.551 0.000 adm3a/display/_COND_40<8>1_F (N13708)
MUXF5:I0->O 1 0.360 0.869 adm3a/display/_COND_40<8>1 (adm3a/display/_COND_40<8>11)
LUT3:I2->O 1 0.551 0.000 adm3a/display/inst_LPM_MUX_f5_G (N13663)
MUXF5:I1->O 3 0.360 0.907 adm3a/display/inst_LPM_MUX_f5 (adm3a/display/curchr<0>)
MULT18X18:A0->P0 51 1.779 2.157 adm3a/display/Mmult__mult0002 (adm3a/display/_mult0002<0>)
LUT2:I1->O 1 0.551 0.000 adm3a/display/Madd__addsub0001_lut<0> (adm3a/display/N2558)
MUXCY:S->O 1 0.500 0.000 adm3a/display/Madd__addsub0001_cy<0> (adm3a/display/Madd__addsub0001_cy<0>)
XORCY:CI->O 176 0.904 2.704 adm3a/display/Madd__addsub0001_xor<1> (adm3a/display/_addsub0001<1>)
LUT4_D:I3->O 17 0.551 1.371 adm3a/display/crom/Mrom_data349_SW0 (N12990)
LUT4:I3->O 7 0.551 1.092 adm3a/display/crom/Mrom_data51 (adm3a/display/N53)
LUT4:I3->O 1 0.551 0.000 adm3a/display/chradr<5>_f5_02_F (N14386)
MUXF5:I0->O 1 0.360 0.827 adm3a/display/chradr<5>_f5_02 (adm3a/display/chradr<5>_f51123)
LUT4:I3->O 1 0.551 0.000 adm3a/display/chradr<8>489_G (N13703)
MUXF5:I1->O 1 0.360 0.869 adm3a/display/chradr<8>489 (adm3a/display/chradr<8>4_map4807)
LUT4:I2->O 1 0.551 0.827 adm3a/display/chradr<8>491 (adm3a/display/chradr<8>112)
LUT4:I3->O 1 0.551 0.000 adm3a/display/mux2_f5_G (N13675)
MUXF5:I1->O 2 0.360 0.903 adm3a/display/mux2_f5 (adm3a/display/N13612)
LUT4:I3->O 1 0.551 0.000 adm3a/display/_mux0000<5>1 (adm3a/display/_mux0000<5>)
FDE:D 0.203 adm3a/display/pixeldata_5
----------------------------------------
Total 33.473ns (14.752ns logic, 18.721ns route)
(44.1% logic, 55.9% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clkdiv_31'
Total number of paths / destination ports: 462 / 433
-------------------------------------------------------------------------
Offset: 10.291ns (Levels of Logic = 7)
Source: waitr (PAD)
Destination: cpu/state_FFd2 (FF)
Destination Clock: clkdiv_31 rising
Data Path: cpu/addr_10 to intc/active_7 Data Path: waitr to cpu/state_FFd2
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
FDE:C->Q 5 0.626 0.842 cpu/addr_10 (cpu/addr_10) IBUF:I->O 13 0.821 1.365 waitr_IBUF (waitr_IBUF)
LUT4:I2->O 1 0.479 0.000 select1/selectc/selectout1511 (N12307) LUT4:I1->O 1 0.551 0.827 cpu/state_FFd8-In8_SW0 (N1768)
MUXF5:I1->O 2 0.314 1.040 select1/selectc/selectout151_f5 (select1/selectc/selectout_map4308) LUT4:I3->O 3 0.551 0.975 cpu/state_FFd8-In8 (N265)
LUT4_D:I0->O 1 0.479 0.704 select1/selectc/selectout169_1 (select1/selectc/selectout169) LUT4:I2->O 1 0.551 1.140 cpu/state_FFd2-In20 (cpu/state_FFd2-In_map3973)
LUT4:I3->O 9 0.479 1.014 intc/_and00011 (intc/_and0001) LUT4:I0->O 1 0.551 0.827 cpu/state_FFd2-In201 (cpu/state_FFd2-In_map4015)
LUT4_D:I2->O 7 0.479 0.929 intc/_not00162 (N202) LUT4:I3->O 1 0.551 0.827 cpu/state_FFd2-In419 (cpu/state_FFd2-In_map4064)
LUT4:I3->O 1 0.479 0.681 intc/_not0016 (intc/_not0016) LUT4:I3->O 1 0.551 0.000 cpu/state_FFd2-In435 (cpu/state_FFd2-In)
FDRE_1:CE 0.524 intc/active_7 FDS:D 0.203 cpu/state_FFd2
---------------------------------------- ----------------------------------------
Total 9.069ns (3.859ns logic, 5.211ns route) Total 10.291ns (4.330ns logic, 5.961ns route)
(42.5% logic, 57.5% route) (42.1% logic, 57.9% route)
==================================================================================================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clock'Timing constraint: Default OFFSET IN BEFORE for Clock 'clock'
Total number of paths / destination ports: 13926 / 607 Total number of paths / destination ports: 413 / 413
--------------------------------------------------------------------------------------------------------------------------------------------------
Offset: 15.913ns (Levels of Logic = 11)Offset: 10.229ns (Levels of Logic = 3)
Source: data<4> (PAD) Source: reset_n (PAD)
Destination: cpu/regfil_5_7 (FF) Destination: adm3a/display/chrcnt_0 (FF)
Destination Clock: clock rising Destination Clock: clock rising
Data Path: data<4> to cpu/regfil_5_7 Data Path: reset_n to adm3a/display/chrcnt_0
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
IOBUF:IO->O 164 0.715 2.513 data_4_IOBUF (N11201) BUFGP:I->O 177 0.401 3.023 reset_n_BUFGP (reset_n_BUFGP)
LUT2:I0->O 23 0.479 1.469 cpu/state_FFd1-In3282 (cpu/_cmp_eq0211) LUT3:I0->O 15 0.551 1.214 adm3a/display/_or00011 (adm3a/display/_or0001)
LUT4:I3->O 11 0.479 0.995 cpu/_cmp_eq00651 (cpu/_cmp_eq0065) LUT4:I3->O 313 0.551 3.463 adm3a/display/_or00021 (adm3a/display/_or0002)
LUT4:I3->O 8 0.479 0.980 cpu/_mux0012<0>311 (N447) FDRE:R 1.026 adm3a/display/chrcnt_0
LUT4:I2->O 1 0.479 0.851 cpu/_mux0013<7>1117_SW0 (N12113)
LUT3_D:I1->O 2 0.479 1.040 cpu/_mux0013<7>1117 (N411)
LUT4_D:I0->LO 1 0.479 0.159 cpu/_mux0013<7>1281 (N12420)
LUT4:I2->O 8 0.479 1.216 cpu/_mux0013<7>120 (N410)
LUT3:I0->O 1 0.479 0.851 cpu/_mux0013<7>8_SW0 (N11497)
LUT4_L:I1->LO 1 0.479 0.159 cpu/_mux0013<7>22 (cpu/_mux0013<7>_map4164)
LUT4:I2->O 1 0.479 0.000 cpu/_mux0013<7>172 (cpu/_mux0013<7>)
FDE:D 0.176 cpu/regfil_5_7
---------------------------------------- ----------------------------------------
Total 15.913ns (5.681ns logic, 10.232ns route) Total 10.229ns (2.529ns logic, 7.700ns route)
(35.7% logic, 64.3% route) (24.7% logic, 75.3% route)
==================================================================================================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectd/_and0000'Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectd/_and0000'
Total number of paths / destination ports: 11 / 11 Total number of paths / destination ports: 14 / 14
--------------------------------------------------------------------------------------------------------------------------------------------------
Offset: 3.372ns (Levels of Logic = 1)Offset: 2.474ns (Levels of Logic = 1)
Source: data<3> (PAD) Source: data<6> (PAD)
Destination: select1/selectd/mask_3 (LATCH) Destination: select1/selectd/mask_6 (LATCH)
Destination Clock: select1/selectd/_and0000 falling Destination Clock: select1/selectd/_and0000 falling
Data Path: data<3> to select1/selectd/mask_3 Data Path: data<6> to select1/selectd/mask_6
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
IOBUF:IO->O 218 0.715 2.481 data_3_IOBUF (N11202) IOBUF:IO->O 19 0.821 1.450 data_6_IOBUF (N12692)
LDCE:D 0.176 select1/selectd/comp_1 LDCE:D 0.203 select1/selectd/mask_6
---------------------------------------- ----------------------------------------
Total 3.372ns (0.891ns logic, 2.481ns route) Total 2.474ns (1.024ns logic, 1.450ns route)
(26.4% logic, 73.6% route) (41.4% logic, 58.6% route)
==================================================================================================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectc/_and0000'Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectc/_and0000'
Total number of paths / destination ports: 14 / 14 Total number of paths / destination ports: 14 / 14
--------------------------------------------------------------------------------------------------------------------------------------------------
Offset: 3.372ns (Levels of Logic = 1)Offset: 2.474ns (Levels of Logic = 1)
Source: data<3> (PAD) Source: data<6> (PAD)
Destination: select1/selectc/mask_3 (LATCH) Destination: select1/selectc/mask_6 (LATCH)
Destination Clock: select1/selectc/_and0000 falling Destination Clock: select1/selectc/_and0000 falling
Data Path: data<3> to select1/selectc/mask_3 Data Path: data<6> to select1/selectc/mask_6
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
IOBUF:IO->O 218 0.715 2.481 data_3_IOBUF (N11202) IOBUF:IO->O 19 0.821 1.450 data_6_IOBUF (N12692)
LDCE:D 0.176 select1/selectc/mask_3 LDCE:D 0.203 select1/selectc/mask_6
---------------------------------------- ----------------------------------------
Total 3.372ns (0.891ns logic, 2.481ns route) Total 2.474ns (1.024ns logic, 1.450ns route)
(26.4% logic, 73.6% route) (41.4% logic, 58.6% route)
==================================================================================================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectb/_and0000'Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectb/_and0000'
Total number of paths / destination ports: 14 / 14 Total number of paths / destination ports: 14 / 14
--------------------------------------------------------------------------------------------------------------------------------------------------
Offset: 3.372ns (Levels of Logic = 1)Offset: 2.474ns (Levels of Logic = 1)
Source: data<3> (PAD) Source: data<6> (PAD)
Destination: select1/selectb/mask_3 (LATCH) Destination: select1/selectb/mask_6 (LATCH)
Destination Clock: select1/selectb/_and0000 falling Destination Clock: select1/selectb/_and0000 falling
Data Path: data<3> to select1/selectb/mask_3 Data Path: data<6> to select1/selectb/mask_6
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
IOBUF:IO->O 218 0.715 2.481 data_3_IOBUF (N11202) IOBUF:IO->O 19 0.821 1.450 data_6_IOBUF (N12692)
LDCE:D 0.176 select1/selectb/comp_1 LDCE:D 0.203 select1/selectb/mask_6
---------------------------------------- ----------------------------------------
Total 3.372ns (0.891ns logic, 2.481ns route) Total 2.474ns (1.024ns logic, 1.450ns route)
(26.4% logic, 73.6% route) (41.4% logic, 58.6% route)
==================================================================================================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selecta/_and0000'Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selecta/_and0000'
Total number of paths / destination ports: 14 / 14 Total number of paths / destination ports: 14 / 14
--------------------------------------------------------------------------------------------------------------------------------------------------
Offset: 3.372ns (Levels of Logic = 1)Offset: 2.474ns (Levels of Logic = 1)
Source: data<3> (PAD) Source: data<6> (PAD)
Destination: select1/selecta/mask_3 (LATCH) Destination: select1/selecta/mask_6 (LATCH)
Destination Clock: select1/selecta/_and0000 falling Destination Clock: select1/selecta/_and0000 falling
Data Path: data<3> to select1/selecta/mask_3 Data Path: data<6> to select1/selecta/mask_6
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
IOBUF:IO->O 218 0.715 2.481 data_3_IOBUF (N11202) IOBUF:IO->O 19 0.821 1.450 data_6_IOBUF (N12692)
LDCE:D 0.176 select1/selecta/mask_3 LDCE:D 0.203 select1/selecta/mask_6
---------------------------------------- ----------------------------------------
Total 3.372ns (0.891ns logic, 2.481ns route) Total 2.474ns (1.024ns logic, 1.450ns route)
(26.4% logic, 73.6% route) (41.4% logic, 58.6% route)
==================================================================================================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'Timing constraint: Default OFFSET OUT AFTER for Clock 'clkdiv_31'
Total number of paths / destination ports: 1340 / 30 Total number of paths / destination ports: 2213 / 30
--------------------------------------------------------------------------------------------------------------------------------------------------
Offset: 17.890ns (Levels of Logic = 10)Offset: 19.654ns (Levels of Logic = 8)
Source: cpu/addr_10 (FF) Source: cpu/addr_4 (FF)
Destination: data<7> (PAD) Destination: data<7> (PAD)
Source Clock: clock rising Source Clock: clkdiv_31 rising
Data Path: cpu/addr_10 to data<7> Data Path: cpu/addr_4 to data<7>
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
FDE:C->Q 5 0.626 0.842 cpu/addr_10 (cpu/addr_10) FDE:C->Q 8 0.720 1.278 cpu/addr_4 (cpu/addr_4)
LUT4:I2->O 1 0.479 0.000 select1/selectc/selectout1511 (N12307) LUT4:I1->O 3 0.551 1.246 select1/selacc426 (select1/selacc4_map4116)
MUXF5:I1->O 2 0.314 1.040 select1/selectc/selectout151_f5 (select1/selectc/selectout_map4308) LUT2:I0->O 3 0.551 1.246 select1/selacc454 (select1/selacc)
LUT4_D:I0->O 1 0.479 0.704 select1/selectc/selectout169_1 (select1/selectc/selectout169) LUT4:I0->O 9 0.551 1.319 select1/selecta/_and0001_inv1 (select1/selecta/_and0001_inv)
LUT4:I3->O 9 0.479 1.250 intc/_and00011 (intc/_and0001) LUT2:I1->O 1 0.551 1.140 N187LogicTrst119 (N187LogicTrst1_map4664)
LUT2:I0->O 8 0.479 1.216 intc/_or0000_inv1 (intc/_or0000_inv) LUT4:I0->O 1 0.551 0.827 N187LogicTrst124 (N187LogicTrst1_map4665)
LUT4:I0->O 1 0.479 0.704 N185LogicTrst1_SW0 (N4909) LUT4:I3->O 16 0.551 1.576 N187LogicTrst141 (N190)
LUT4:I3->O 14 0.479 1.032 N185LogicTrst1 (N1913) LUT3:I0->O 1 0.551 0.801 N187LogicTrst1211 (data_7_IOBUF)
LUT4:I3->O 1 0.479 0.740 N185LogicTrst136_SW1 (N12137) IOBUF:I->IO 5.644 data_7_IOBUF (data<7>)
LUT4:I2->O 1 0.479 0.681 N185LogicTrst136 (data_7_IOBUF)
IOBUF:I->IO 4.909 data_7_IOBUF (data<7>)
---------------------------------------- ----------------------------------------
Total 17.890ns (9.681ns logic, 8.209ns route) Total 19.654ns (10.221ns logic, 9.433ns route)
(54.1% logic, 45.9% route) (52.0% logic, 48.0% route)
==================================================================================================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectc/_and0000'Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'
Total number of paths / destination ports: 552 / 8 Total number of paths / destination ports: 12 / 12
--------------------------------------------------------------------------------------------------------------------------------------------------
Offset: 18.039ns (Levels of Logic = 10)Offset: 13.243ns (Levels of Logic = 5)
Source: select1/selectc/comp_0 (LATCH) Source: adm3a/datao_7 (FF)
Destination: data<7> (PAD) Destination: data<7> (PAD)
Source Clock: select1/selectc/_and0000 falling Source Clock: clock falling
Data Path: select1/selectc/comp_0 to data<7> Data Path: adm3a/datao_7 to data<7>
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
LDCE:G->Q 3 0.551 1.066 select1/selectc/comp_0 (select1/selectc/comp_0) FDE_1:C->Q 1 0.720 0.869 adm3a/datao_7 (adm3a/datao_7)
LUT4:I0->O 1 0.479 0.000 select1/selectc/selectout1511 (N12307) LUT4:I2->O 1 0.551 0.996 N187LogicTrst69 (N187LogicTrst_map4691)
MUXF5:I1->O 2 0.314 1.040 select1/selectc/selectout151_f5 (select1/selectc/selectout_map4308) LUT3:I1->O 1 0.551 1.140 N187LogicTrst109_SW0 (N14179)
LUT4_D:I0->O 1 0.479 0.704 select1/selectc/selectout169_1 (select1/selectc/selectout169) LUT4:I0->O 1 0.551 0.869 N187LogicTrst109 (N187LogicTrst_map4696)
LUT4:I3->O 9 0.479 1.250 intc/_and00011 (intc/_and0001) LUT3:I2->O 1 0.551 0.801 N187LogicTrst1211 (data_7_IOBUF)
LUT2:I0->O 8 0.479 1.216 intc/_or0000_inv1 (intc/_or0000_inv) IOBUF:I->IO 5.644 data_7_IOBUF (data<7>)
LUT4:I0->O 1 0.479 0.704 N185LogicTrst1_SW0 (N4909)
LUT4:I3->O 14 0.479 1.032 N185LogicTrst1 (N1913)
LUT4:I3->O 1 0.479 0.740 N185LogicTrst136_SW1 (N12137)
LUT4:I2->O 1 0.479 0.681 N185LogicTrst136 (data_7_IOBUF)
IOBUF:I->IO 4.909 data_7_IOBUF (data<7>)
---------------------------------------- ----------------------------------------
Total 18.039ns (9.606ns logic, 8.433ns route) Total 13.243ns (8.568ns logic, 4.675ns route)
(53.3% logic, 46.7% route) (64.7% logic, 35.3% route)
==================================================================================================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectb/_and0000'Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectb/_and0000'
Total number of paths / destination ports: 648 / 8 Total number of paths / destination ports: 840 / 8
--------------------------------------------------------------------------------------------------------------------------------------------------
Offset: 15.904ns (Levels of Logic = 9)Offset: 17.126ns (Levels of Logic = 8)
Source: select1/selectb/comp_2 (LATCH) Source: select1/selectb/comp_1 (LATCH)
Destination: data<7> (PAD) Destination: data<7> (PAD)
Source Clock: select1/selectb/_and0000 falling Source Clock: select1/selectb/_and0000 falling
Data Path: select1/selectb/comp_2 to data<7> Data Path: select1/selectb/comp_1 to data<7>
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
LDCE:G->Q 3 0.551 1.066 select1/selectb/comp_2 (select1/selectb/comp_2) LDCE:G->Q 3 0.633 1.246 select1/selectb/comp_1 (select1/selectb/comp_1)
LUT4:I0->O 1 0.479 0.000 select1/select2791 (N12279) LUT4:I0->O 1 0.551 0.000 select1/select248_SW02 (N14530)
MUXF5:I1->O 1 0.314 0.976 select1/select279_f5 (select1/select2_map1830) MUXF5:I0->O 2 0.360 1.072 select1/select248_SW0_f5 (N13802)
LUT4:I0->O 1 0.479 0.740 select1/select2169 (select1/select2_map1857) LUT4:I1->O 1 0.551 0.000 select1/select2482 (N14532)
LUT4:I2->O 4 0.479 0.838 select1/select2195 (ramsel) MUXF5:I0->O 2 0.360 1.216 select1/select248_f5 (select1/select2_map4289)
LUT4:I2->O 1 0.479 0.704 N185LogicTrst1_SW0 (N4909) LUT4:I0->O 9 0.551 1.463 ram/_and0000_inv1 (ram/_and0000_inv)
LUT4:I3->O 14 0.479 1.032 N185LogicTrst1 (N1913) LUT4:I0->O 16 0.551 1.576 N187LogicTrst141 (N190)
LUT4:I3->O 1 0.479 0.740 N185LogicTrst136_SW1 (N12137) LUT3:I0->O 1 0.551 0.801 N187LogicTrst1211 (data_7_IOBUF)
LUT4:I2->O 1 0.479 0.681 N185LogicTrst136 (data_7_IOBUF) IOBUF:I->IO 5.644 data_7_IOBUF (data<7>)
IOBUF:I->IO 4.909 data_7_IOBUF (data<7>)
---------------------------------------- ----------------------------------------
Total 15.904ns (9.127ns logic, 6.777ns route) Total 17.126ns (9.752ns logic, 7.374ns route)
(57.4% logic, 42.6% route) (56.9% logic, 43.1% route)
==================================================================================================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'reset'Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selecta/_and0000'
Total number of paths / destination ports: 24 / 6 Total number of paths / destination ports: 840 / 8
--------------------------------------------------------------------------------------------------------------------------------------------------
Offset: 13.765ns (Levels of Logic = 7)Offset: 18.117ns (Levels of Logic = 9)
Source: select1/selectd/datai_7 (LATCH) Source: select1/selecta/mask_1 (LATCH)
Destination: data<6> (PAD)
Source Clock: select1/selecta/_and0000 falling
Data Path: select1/selecta/mask_1 to data<6>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LDCE:G->Q 7 0.633 1.405 select1/selecta/mask_1 (select1/selecta/mask_1)
LUT4:I0->O 1 0.551 0.000 _and0000_inv181 (N14508)
MUXF5:I1->O 1 0.360 1.140 _and0000_inv18_f5 (_and0000_inv_map4593)
LUT4:I0->O 1 0.551 1.140 _and0000_inv108 (_and0000_inv_map4620)
LUT4:I0->O 9 0.551 1.319 _and0000_inv211 (_and0000_inv)
LUT4:I1->O 1 0.551 0.869 N199LogicTrst65 (N199LogicTrst_map4415)
LUT3:I2->O 1 0.551 1.140 N199LogicTrst99_SW0 (N14163)
LUT4:I0->O 1 0.551 0.000 N199LogicTrst1111 (N14501)
MUXF5:I0->O 1 0.360 0.801 N199LogicTrst111_f5 (data_1_IOBUF)
IOBUF:I->IO 5.644 data_1_IOBUF (data<1>)
----------------------------------------
Total 18.117ns (10.303ns logic, 7.814ns route)
(56.9% logic, 43.1% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectc/_and0000'
Total number of paths / destination ports: 648 / 8
-------------------------------------------------------------------------
Offset: 18.861ns (Levels of Logic = 8)
Source: select1/selectc/mask_1 (LATCH)
Destination: data<7> (PAD) Destination: data<7> (PAD)
Source Clock: reset rising Source Clock: select1/selectc/_and0000 falling
Data Path: select1/selectd/datai_7 to data<7> Data Path: select1/selectc/mask_1 to data<7>
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
LDE_1:G->Q 1 0.551 0.704 select1/selectd/datai_7 (select1/selectd/datai_7) LDCE:G->Q 7 0.633 1.405 select1/selectc/mask_1 (select1/selectc/mask_1)
LUT4:I3->O 1 0.479 0.851 N185LogicTrst29_SW0 (N11753) LUT4:I0->O 1 0.551 0.000 select1/selectc/selectout791 (N14518)
LUT4:I1->O 1 0.479 0.740 N185LogicTrst29 (N185LogicTrst_map3906) MUXF5:I1->O 1 0.360 1.140 select1/selectc/selectout79_f5 (select1/selectc/selectout_map4980)
LUT4:I2->O 1 0.479 0.976 N185LogicTrst60 (N185LogicTrst_map3910) LUT4_D:I0->O 3 0.551 0.975 select1/selectc/selectout169 (select1/selectc/selectout_map5007)
LUT4:I0->O 1 0.479 0.740 N185LogicTrst93 (N185LogicTrst_map3916) LUT4:I2->O 25 0.551 2.152 intc/_not0027_SW0 (intc/_and0001)
LUT4:I2->O 1 0.479 0.740 N185LogicTrst136_SW1 (N12137) LUT2:I0->O 1 0.551 0.869 intc/_or0000_inv1 (intc/_or0000_inv)
LUT4:I2->O 1 0.479 0.681 N185LogicTrst136 (data_7_IOBUF) LUT4:I2->O 16 0.551 1.576 N187LogicTrst141 (N190)
IOBUF:I->IO 4.909 data_7_IOBUF (data<7>) LUT3:I0->O 1 0.551 0.801 N187LogicTrst1211 (data_7_IOBUF)
IOBUF:I->IO 5.644 data_7_IOBUF (data<7>)
---------------------------------------- ----------------------------------------
Total 13.765ns (8.334ns logic, 5.431ns route) Total 18.861ns (9.943ns logic, 8.918ns route)
(60.5% logic, 39.5% route) (52.7% logic, 47.3% route)
==================================================================================================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selecta/_and0000'Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectd/_and0000'
Total number of paths / destination ports: 840 / 8 Total number of paths / destination ports: 459 / 8
--------------------------------------------------------------------------------------------------------------------------------------------------
Offset: 16.261ns (Levels of Logic = 9)Offset: 18.964ns (Levels of Logic = 9)
Source: select1/selecta/mask_1 (LATCH) Source: select1/selectd/mask_1 (LATCH)
Destination: data<7> (PAD) Destination: data<7> (PAD)
Source Clock: select1/selecta/_and0000 falling Source Clock: select1/selectd/_and0000 falling
Data Path: select1/selectd/mask_1 to data<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LDCE:G->Q 7 0.633 1.405 select1/selectd/mask_1 (select1/selectd/mask_1)
LUT4:I0->O 1 0.551 0.000 select1/selectd/selectout791 (N14485)
MUXF5:I1->O 1 0.360 1.140 select1/selectd/selectout79_f5 (select1/selectd/selectout_map4243)
LUT4:I0->O 3 0.551 0.975 select1/selectd/selectout169 (select1/selectd/selectout_map4270)
LUT3:I2->O 12 0.551 1.144 select1/selectd/selectout183 (trmsel)
LUT4:I3->O 1 0.551 0.996 N187LogicTrst69 (N187LogicTrst_map4691)
LUT3:I1->O 1 0.551 1.140 N187LogicTrst109_SW0 (N14179)
LUT4:I0->O 1 0.551 0.869 N187LogicTrst109 (N187LogicTrst_map4696)
LUT3:I2->O 1 0.551 0.801 N187LogicTrst1211 (data_7_IOBUF)
IOBUF:I->IO 5.644 data_7_IOBUF (data<7>)
----------------------------------------
Total 18.964ns (10.494ns logic, 8.470ns route)
(55.3% logic, 44.7% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'reset_n'
Total number of paths / destination ports: 32 / 8
-------------------------------------------------------------------------
Offset: 14.894ns (Levels of Logic = 7)
Source: select1/selectb/datai_6 (LATCH)
Destination: data<6> (PAD)
Source Clock: reset_n falling
Data Path: select1/selecta/mask_1 to data<7> Data Path: select1/selectb/datai_6 to data<6>
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
LDCE:G->Q 6 0.551 1.148 select1/selecta/mask_1 (select1/selecta/mask_1) LDE_1:G->Q 1 0.633 0.996 select1/selectb/datai_6 (select1/selectb/datai_6)
LUT4:I0->O 1 0.479 0.000 _and0000_inv181 (N12287) LUT3:I1->O 1 0.551 0.869 N189LogicTrst15 (N189LogicTrst_map4564)
MUXF5:I1->O 1 0.314 0.976 _and0000_inv18_f5 (_and0000_inv_map1867) LUT4:I2->O 1 0.551 0.827 N189LogicTrst47 (N189LogicTrst_map4572)
LUT4:I0->O 1 0.479 0.976 _and0000_inv108 (_and0000_inv_map1894) LUT4:I3->O 1 0.551 0.869 N189LogicTrst80 (N189LogicTrst_map4578)
LUT4:I0->O 10 0.479 1.023 _and0000_inv211 (_and0000_inv) LUT3:I2->O 1 0.551 1.140 N189LogicTrst114_SW0 (N14175)
LUT3:I2->O 1 0.479 0.851 N185LogicTrst93_SW0 (N11757) LUT4:I0->O 1 0.551 0.000 N189LogicTrst1261 (N14507)
LUT4:I1->O 1 0.479 0.740 N185LogicTrst93 (N185LogicTrst_map3916) MUXF5:I0->O 1 0.360 0.801 N189LogicTrst126_f5 (data_6_IOBUF)
LUT4:I2->O 1 0.479 0.740 N185LogicTrst136_SW1 (N12137) IOBUF:I->IO 5.644 data_6_IOBUF (data<6>)
LUT4:I2->O 1 0.479 0.681 N185LogicTrst136 (data_7_IOBUF)
IOBUF:I->IO 4.909 data_7_IOBUF (data<7>)
---------------------------------------- ----------------------------------------
Total 16.261ns (9.127ns logic, 7.134ns route) Total 14.894ns (9.392ns logic, 5.502ns route)
(56.1% logic, 43.9% route) (63.1% logic, 36.9% route)
==================================================================================================================================================
CPU : 113.61 / 113.84 s | Elapsed : 114.00 / 114.00 sCPU : 257.34 / 257.59 s | Elapsed : 258.00 / 258.00 s
-->-->
Total memory usage is 200528 kilobytesTotal memory usage is 232272 kilobytes
Number of errors : 0 ( 0 filtered)Number of errors : 0 ( 0 filtered)
Number of warnings : 12 ( 0 filtered)Number of warnings : 167 ( 0 filtered)
Number of infos : 5 ( 0 filtered)Number of infos : 10 ( 0 filtered)
