| Line 26... |
Line 26... |
readio, // Read I/O space
|
readio, // Read I/O space
|
writeio, // Write I/O space
|
writeio, // Write I/O space
|
intr, // Interrupt request
|
intr, // Interrupt request
|
inta, // Interrupt request
|
inta, // Interrupt request
|
waitr, // Wait request
|
waitr, // Wait request
|
reset, // Reset
|
r, g, b, // vga colors
|
|
hsync_n, // vga horizontal sync negative
|
|
vsync_n, // vga vertical sync negative
|
|
reset_n, // Reset
|
clock); // System clock
|
clock); // System clock
|
|
|
output [15:0] addr;
|
output [15:0] addr;
|
inout [7:0] data;
|
inout [7:0] data;
|
output readmem;
|
output readmem;
|
| Line 38... |
Line 41... |
output readio;
|
output readio;
|
output writeio;
|
output writeio;
|
output intr;
|
output intr;
|
output inta;
|
output inta;
|
input waitr;
|
input waitr;
|
input reset;
|
output [2:0] r, g, b; // R,G,B color output buses
|
|
output hsync_n; // horizontal sync pulse
|
|
output vsync_n; // vertical sync pulse
|
|
input reset_n;
|
input clock;
|
input clock;
|
|
|
|
reg [7:0] clkdiv;
|
|
wire clocki;
|
|
wire reset;
|
|
|
|
initial clkdiv = 0;
|
|
|
|
// divide down the clock so we can debug
|
|
always @(posedge clock) clkdiv <= clkdiv+1; // count
|
|
assign clocki = clkdiv[3]; // pick off top bit as internal clock
|
|
// assign clocki = clock;
|
|
|
|
//
|
|
// Instantiations
|
|
//
|
|
|
// selector block, we only use select 1, 2 and 3
|
// selector block, we only use select 1, 2 and 3
|
select select1(addr, data, readio, writeio, romsel, ramsel, intsel,
|
select select1(addr, data, readio, writeio, romsel, ramsel, intsel,
|
select4, bootstrap, clock, reset);
|
trmsel, bootstrap, clocki, reset);
|
|
|
|
// 8080 CPU
|
cpu8080 cpu(addr, data, readmem, writemem, readio, writeio, intr, inta, waitr,
|
cpu8080 cpu(addr, data, readmem, writemem, readio, writeio, intr, inta, waitr,
|
reset, clock);
|
reset, clocki);
|
|
// assign readmem = 0;
|
|
// assign writemem = 0;
|
|
// assign readio = 0;
|
|
// assign writeio = 0;
|
|
// assign inta = 0;
|
|
// assign addr = 0;
|
|
|
|
// Program rom
|
rom rom(addr[9:0], data, romsel&readmem); // unclocked rom
|
rom rom(addr[9:0], data, romsel&readmem); // unclocked rom
|
|
|
// neg clocked ram
|
// neg clocked ram
|
ram ram(addr[9:0], data, ramsel, readmem, writemem, bootstrap, clock);
|
ram ram(addr[9:0], data, ramsel, readmem, writemem, bootstrap, clocki);
|
|
|
// neg clocked interrupt controller
|
// neg clocked interrupt controller
|
intcontrol intc(addr[2:0], data, writeio, readio, intsel, intr, inta, int0, int1,
|
intcontrol intc(addr[2:0], data, writeio, readio, intsel, intr, inta, int0, int1,
|
int2, int3, int4, int5, int6, int7, reset, clock);
|
int2, int3, int4, int5, int6, int7, reset, clocki);
|
|
|
|
// ADM3A dumb terminal
|
|
terminal adm3a(addr[0], data, writeio, readio, trmsel, r, g, b, hsync_n, vsync_n,
|
|
reset, clock);
|
|
|
|
// generate reset
|
|
assign reset = !reset_n;
|
|
|
// pull up unused interrupt lines
|
// pull up unused interrupt lines
|
assign int0 = 1;
|
assign int0 = 1;
|
assign int1 = 1;
|
assign int1 = 1;
|
assign int2 = 1;
|
assign int2 = 1;
|
assign int3 = 1;
|
assign int3 = 1;
|
assign int4 = 1;
|
assign int4 = 1;
|
assign int5 = 1;
|
assign int5 = 1;
|
assign int6 = 1;
|
assign int6 = 1;
|
assign int7 = 1;
|
assign int7 = 1;
|
// fake input device, always returns $42
|
|
assign data = readio ? 8'h42: 8'bz;
|
|
|
|
endmodule
|
endmodule
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
