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[/] [cpu8080/] [trunk/] [project/] [testbench.v] - Diff between revs 18 and 24

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Rev 18 Rev 24
Line 66... Line 66...
   // 8080 CPU
   // 8080 CPU
   cpu8080 cpu(addr, data, readmem, writemem, readio, writeio, intr, inta, waitr,
   cpu8080 cpu(addr, data, readmem, writemem, readio, writeio, intr, inta, waitr,
               reset, clock);
               reset, clock);
 
 
   // Program rom
   // Program rom
   rom rom(addr[9:0], data, romsel&readmem); // unclocked rom
   rom rom(addr[10:0], data, romsel&readmem); // unclocked rom
 
 
   // neg clocked ram
   // neg clocked ram
   ram ram(addr[9:0], data, ramsel, readmem, writemem, bootstrap, clock);
   ram ram(addr[9:0], data, ramsel, readmem, writemem, bootstrap, clock);
 
 
   // neg clocked interrupt controller
   // neg clocked interrupt controller
Line 546... Line 546...
// enable outputs only.
// enable outputs only.
//
//
 
 
module rom(addr, data, dataeno);
module rom(addr, data, dataeno);
 
 
   input [9:0] addr;
   input [10:0] addr;
   inout [7:0] data;
   inout [7:0] data;
   input dataeno;
   input dataeno;
 
 
   reg [7:0] datao;
   reg [7:0] datao;
 
 

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