| Line 7... |
Line 7... |
C:/Xilinx/ISEexamples/cpu8080/cpu8080.ise -intstyle ise -p xc3s1000-ft256-4 -cm
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C:/Xilinx/ISEexamples/cpu8080/cpu8080.ise -intstyle ise -p xc3s1000-ft256-4 -cm
|
area -pr b -k 4 -c 100 -o testbench_map.ncd testbench.ngd testbench.pcf
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area -pr b -k 4 -c 100 -o testbench_map.ncd testbench.ngd testbench.pcf
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Target Device : xc3s1000
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Target Device : xc3s1000
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Target Package : ft256
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Target Package : ft256
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Target Speed : -4
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Target Speed : -4
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Mapper Version : spartan3 -- $Revision: 1.1.1.1 $
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Mapper Version : spartan3 -- $Revision: 1.1.1.2 $
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Mapped Date : Wed Nov 01 08:45:26 2006
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Mapped Date : Sat Nov 11 00:49:29 2006
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|
|
Design Summary
|
Design Summary
|
--------------
|
--------------
|
Number of errors: 0
|
Number of errors: 0
|
Number of warnings: 9
|
Number of warnings: 10
|
Logic Utilization:
|
Logic Utilization:
|
Total Number Slice Registers: 890 out of 15,360 5%
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Total Number Slice Registers: 683 out of 15,360 4%
|
Number used as Flip Flops: 802
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Number used as Flip Flops: 595
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Number used as Latches: 88
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Number used as Latches: 88
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Number of 4 input LUTs: 3,884 out of 15,360 25%
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Number of 4 input LUTs: 4,208 out of 15,360 27%
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Logic Distribution:
|
Logic Distribution:
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Number of occupied Slices: 3,425 out of 7,680 44%
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Number of occupied Slices: 3,312 out of 7,680 43%
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Number of Slices containing only related logic: 3,425 out of 3,425 100%
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Number of Slices containing only related logic: 3,312 out of 3,312 100%
|
Number of Slices containing unrelated logic: 0 out of 3,425 0%
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Number of Slices containing unrelated logic: 0 out of 3,312 0%
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*See NOTES below for an explanation of the effects of unrelated logic
|
*See NOTES below for an explanation of the effects of unrelated logic
|
Total Number 4 input LUTs: 5,760 out of 15,360 37%
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Total Number 4 input LUTs: 6,094 out of 15,360 39%
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Number used as logic: 3,884
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Number used as logic: 4,208
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Number used as a route-thru: 196
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Number used as a route-thru: 206
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Number used for Dual Port RAMs: 1,680
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Number used for Dual Port RAMs: 1,680
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(Two LUTs used per Dual Port RAM)
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(Two LUTs used per Dual Port RAM)
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Number of bonded IOBs: 44 out of 173 25%
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Number of bonded IOBs: 54 out of 173 31%
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IOB Flip Flops: 9
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IOB Flip Flops: 11
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Number of Block RAMs: 2 out of 24 8%
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Number of Block RAMs: 3 out of 24 12%
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Number of MULT18X18s: 1 out of 24 4%
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Number of MULT18X18s: 1 out of 24 4%
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Number of GCLKs: 3 out of 8 37%
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Number of GCLKs: 2 out of 8 25%
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|
|
Total equivalent gate count for design: 278,010
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Total equivalent gate count for design: 344,099
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Additional JTAG gate count for IOBs: 2,112
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Additional JTAG gate count for IOBs: 2,592
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Peak Memory Usage: 194 MB
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Peak Memory Usage: 197 MB
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NOTES:
|
NOTES:
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|
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Related logic is defined as being logic that shares connectivity - e.g. two
|
Related logic is defined as being logic that shares connectivity - e.g. two
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LUTs are "related" if they share common inputs. When assembling slices,
|
LUTs are "related" if they share common inputs. When assembling slices,
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| Line 87... |
Line 87... |
adm3a/display/inst_Mram_mem2100/SPO,
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adm3a/display/inst_Mram_mem2100/SPO,
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adm3a/display/inst_Mram_mem3100/SPO,
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adm3a/display/inst_Mram_mem3100/SPO,
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adm3a/display/inst_Mram_mem4100/SPO,
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adm3a/display/inst_Mram_mem4100/SPO,
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adm3a/display/inst_Mram_mem5100/SPO
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adm3a/display/inst_Mram_mem5100/SPO
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To see the details of these warning messages, please use the -detail switch.
|
To see the details of these warning messages, please use the -detail switch.
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WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
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symbol "physical_group_clkdiv<3>/clkdiv_3_BUFG" (output signal=clkdiv<3>) has
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a mix of clock and non-clock loads. The non-clock loads are:
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Pin LI of Mcount_clkdiv_xor<3>
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WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFGMUX
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WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFGMUX
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symbol "physical_group_reset_n_BUFGP/reset_n_BUFGP/BUFG" (output
|
symbol "physical_group_reset_n_BUFGP/reset_n_BUFGP/BUFG" (output
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signal=reset_n_BUFGP) has a mix of clock and non-clock loads. Some of the
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signal=reset_n_BUFGP) has a mix of clock and non-clock loads. Some of the
|
non-clock loads are (maximum of 5 listed):
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non-clock loads are (maximum of 5 listed):
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Pin PRE of cpu/ei
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Pin CLR of cpu/readmem
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Pin CE of cpu/carry
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Pin CLR of cpu/inta
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Pin CE of cpu/addr_0
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Pin CE of cpu/addr_0
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Pin CE of cpu/addr_1
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Pin CE of cpu/addr_1
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Pin CE of cpu/addr_2
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Pin CE of cpu/addr_2
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WARNING:Pack:266 - The function generator adm3a/display/chradr<4>8 failed to
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WARNING:Pack:266 - The function generator adm3a/display/chradr<4>81 failed to
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merge with F5 multiplexer adm3a/display/chradr<5>_f5_35. There is a conflict
|
merge with F5 multiplexer adm3a/display/chradr<5>_f5_62. There is a conflict
|
for the FXMUX. The design will exhibit suboptimal timing.
|
for the FXMUX. The design will exhibit suboptimal timing.
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is
|
WARNING:Pack:266 - The function generator cpu/_mux0003_SW1 failed to merge with
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|
F5 multiplexer cpu/_mux0003. There is a conflict for the FXMUX. The design
|
|
will exhibit suboptimal timing.
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WARNING:Pack:266 - The function generator cpu/_mux0003_SW1 failed to merge with
|
|
F5 multiplexer cpu/_mux00071_f5. There is a conflict for the FXMUX. The
|
|
design will exhibit suboptimal timing.
|
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
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sourced by a combinatorial pin. This is not good design practice. Use the CE
|
pin to control the loading of data into the flip-flop.
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pin to control the loading of data into the flip-flop.
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
pin to control the loading of data into the flip-flop.
|
pin to control the loading of data into the flip-flop.
|
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is
|
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
pin to control the loading of data into the flip-flop.
|
pin to control the loading of data into the flip-flop.
|
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
pin to control the loading of data into the flip-flop.
|
pin to control the loading of data into the flip-flop.
|
|
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Section 3 - Informational
|
Section 3 - Informational
|
-------------------------
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-------------------------
|
INFO:MapLib:562 - No environment variables are currently set.
|
INFO:MapLib:562 - No environment variables are currently set.
|
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
|
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
|
Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
|
Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
|
BUFG symbol "clkdiv_3_BUFG" (output signal=clkdiv<3>),
|
|
BUFGP symbol "clock_BUFGP" (output signal=clock_BUFGP),
|
BUFGP symbol "clock_BUFGP" (output signal=clock_BUFGP),
|
BUFGP symbol "reset_n_BUFGP" (output signal=reset_n_BUFGP)
|
BUFGP symbol "reset_n_BUFGP" (output signal=reset_n_BUFGP)
|
INFO:LIT:244 - All of the single ended outputs in this design are using slew
|
INFO:LIT:244 - All of the single ended outputs in this design are using slew
|
rate limited output drivers. The delay on speed critical single ended outputs
|
rate limited output drivers. The delay on speed critical single ended outputs
|
can be dramatically reduced by designating them as fast outputs in the
|
can be dramatically reduced by designating them as fast outputs in the
|
| Line 190... |
Line 191... |
| data<3> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
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| data<3> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
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| data<4> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
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| data<4> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
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| data<5> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
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| data<5> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
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| data<6> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
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| data<6> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
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| data<7> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
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| data<7> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
|
|
| diag<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| diag<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| diag<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| diag<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| diag<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| diag<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| diag<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| diag<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| g<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| g<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| g<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| g<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| g<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| g<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| hsync_n | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | |
|
| hsync_n | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | |
|
| inta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| inta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| intr | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| intr | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| ps2_clk | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD |
|
|
| ps2_data | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD |
|
| r<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| r<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| r<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| r<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| r<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| r<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| readio | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| readio | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| readmem | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| readmem | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| reset_n | IOB | INPUT | LVCMOS25 | | | | | |
|
| reset_n | IOB | INPUT | LVCMOS25 | | | | | |
|
| vsync_n | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| vsync_n | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| waitr | IOB | INPUT | LVCMOS25 | | | | | |
|
| waitr | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| writeio | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| writeio | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| writemem | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
| writemem | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
+------------------------------------------------------------------------------------------------------------------------+
|
+------------------------------------------------------------------------------------------------------------------------+
|
|
|
Section 7 - RPMs
|
Section 7 - RPMs
|
