| Line 7... |
Line 7... |
C:/Xilinx/ISEexamples/cpu8080/cpu8080.ise -intstyle ise -p xc3s1000-ft256-4 -cm
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C:/Xilinx/ISEexamples/cpu8080/cpu8080.ise -intstyle ise -p xc3s1000-ft256-4 -cm
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area -pr b -k 4 -c 100 -o testbench_map.ncd testbench.ngd testbench.pcf
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area -pr b -k 4 -c 100 -o testbench_map.ncd testbench.ngd testbench.pcf
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Target Device : xc3s1000
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Target Device : xc3s1000
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Target Package : ft256
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Target Package : ft256
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Target Speed : -4
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Target Speed : -4
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Mapper Version : spartan3 -- $Revision: 1.1.1.2 $
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Mapper Version : spartan3 -- $Revision: 1.1.1.3 $
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Mapped Date : Sat Nov 11 00:49:29 2006
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Mapped Date : Wed Nov 15 08:50:16 2006
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|
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Design Summary
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Design Summary
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--------------
|
--------------
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Number of errors: 0
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Number of errors: 0
|
Number of warnings: 10
|
Number of warnings: 13
|
Logic Utilization:
|
Logic Utilization:
|
Total Number Slice Registers: 683 out of 15,360 4%
|
Total Number Slice Registers: 745 out of 15,360 4%
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Number used as Flip Flops: 595
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Number used as Flip Flops: 657
|
Number used as Latches: 88
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Number used as Latches: 88
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Number of 4 input LUTs: 4,208 out of 15,360 27%
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Number of 4 input LUTs: 4,391 out of 15,360 28%
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Logic Distribution:
|
Logic Distribution:
|
Number of occupied Slices: 3,312 out of 7,680 43%
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Number of occupied Slices: 3,458 out of 7,680 45%
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Number of Slices containing only related logic: 3,312 out of 3,312 100%
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Number of Slices containing only related logic: 3,458 out of 3,458 100%
|
Number of Slices containing unrelated logic: 0 out of 3,312 0%
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Number of Slices containing unrelated logic: 0 out of 3,458 0%
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*See NOTES below for an explanation of the effects of unrelated logic
|
*See NOTES below for an explanation of the effects of unrelated logic
|
Total Number 4 input LUTs: 6,094 out of 15,360 39%
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Total Number 4 input LUTs: 6,313 out of 15,360 41%
|
Number used as logic: 4,208
|
Number used as logic: 4,391
|
Number used as a route-thru: 206
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Number used as a route-thru: 242
|
Number used for Dual Port RAMs: 1,680
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Number used for Dual Port RAMs: 1,680
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(Two LUTs used per Dual Port RAM)
|
(Two LUTs used per Dual Port RAM)
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Number of bonded IOBs: 54 out of 173 31%
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Number of bonded IOBs: 54 out of 173 31%
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IOB Flip Flops: 11
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IOB Flip Flops: 11
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Number of Block RAMs: 3 out of 24 12%
|
Number of Block RAMs: 4 out of 24 16%
|
Number of MULT18X18s: 1 out of 24 4%
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Number of MULT18X18s: 2 out of 24 8%
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Number of GCLKs: 2 out of 8 25%
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Number of GCLKs: 2 out of 8 25%
|
|
|
Total equivalent gate count for design: 344,099
|
Total equivalent gate count for design: 415,496
|
Additional JTAG gate count for IOBs: 2,592
|
Additional JTAG gate count for IOBs: 2,592
|
Peak Memory Usage: 197 MB
|
Peak Memory Usage: 199 MB
|
|
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NOTES:
|
NOTES:
|
|
|
Related logic is defined as being logic that shares connectivity - e.g. two
|
Related logic is defined as being logic that shares connectivity - e.g. two
|
LUTs are "related" if they share common inputs. When assembling slices,
|
LUTs are "related" if they share common inputs. When assembling slices,
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| Line 96... |
Line 96... |
Pin CLR of cpu/readmem
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Pin CLR of cpu/readmem
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Pin CLR of cpu/inta
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Pin CLR of cpu/inta
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Pin CE of cpu/addr_0
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Pin CE of cpu/addr_0
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Pin CE of cpu/addr_1
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Pin CE of cpu/addr_1
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Pin CE of cpu/addr_2
|
Pin CE of cpu/addr_2
|
WARNING:Pack:266 - The function generator adm3a/display/chradr<4>81 failed to
|
WARNING:Pack:266 - The function generator adm3a/display/chradr<5>35 failed to
|
merge with F5 multiplexer adm3a/display/chradr<5>_f5_62. There is a conflict
|
merge with F5 multiplexer adm3a/display/chradr<6>_f5_3. There is a conflict
|
for the FXMUX. The design will exhibit suboptimal timing.
|
for the FXMUX. The design will exhibit suboptimal timing.
|
WARNING:Pack:266 - The function generator cpu/_mux0003_SW1 failed to merge with
|
WARNING:Pack:266 - The function generator cpu/_mux0003_SW1 failed to merge with
|
F5 multiplexer cpu/_mux0003. There is a conflict for the FXMUX. The design
|
F5 multiplexer cpu/_mux0003. There is a conflict for the FXMUX. The design
|
will exhibit suboptimal timing.
|
will exhibit suboptimal timing.
|
WARNING:Pack:266 - The function generator cpu/_mux0003_SW1 failed to merge with
|
WARNING:Pack:266 - The function generator cpu/_mux0003_SW1 failed to merge with
|
F5 multiplexer cpu/_mux00071_f5. There is a conflict for the FXMUX. The
|
F5 multiplexer cpu/_mux00071_f5. There is a conflict for the FXMUX. The
|
design will exhibit suboptimal timing.
|
design will exhibit suboptimal timing.
|
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is
|
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
pin to control the loading of data into the flip-flop.
|
pin to control the loading of data into the flip-flop.
|
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is
|
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
pin to control the loading of data into the flip-flop.
|
pin to control the loading of data into the flip-flop.
|
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is
|
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
pin to control the loading of data into the flip-flop.
|
pin to control the loading of data into the flip-flop.
|
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is
|
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
pin to control the loading of data into the flip-flop.
|
pin to control the loading of data into the flip-flop.
|
|
WARNING:PhysDesignRules:812 - Dangling pin on
|
|
block::
|
|
6A>.
|
|
WARNING:PhysDesignRules:812 - Dangling pin on
|
|
block::
|
|
6A>.
|
|
WARNING:PhysDesignRules:812 - Dangling pin on
|
|
block::
|
|
6A>.
|
|
|
Section 3 - Informational
|
Section 3 - Informational
|
-------------------------
|
-------------------------
|
INFO:MapLib:562 - No environment variables are currently set.
|
INFO:MapLib:562 - No environment variables are currently set.
|
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
|
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
|
