| Line 7... |
Line 7... |
C:/Xilinx/ISEexamples/cpu8080/cpu8080.ise -intstyle ise -p xc3s1000-ft256-4 -cm
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C:/Xilinx/ISEexamples/cpu8080/cpu8080.ise -intstyle ise -p xc3s1000-ft256-4 -cm
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area -pr b -k 4 -c 100 -o testbench_map.ncd testbench.ngd testbench.pcf
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area -pr b -k 4 -c 100 -o testbench_map.ncd testbench.ngd testbench.pcf
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Target Device : xc3s1000
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Target Device : xc3s1000
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Target Package : ft256
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Target Package : ft256
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Target Speed : -4
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Target Speed : -4
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Mapper Version : spartan3 -- $Revision: 1.1.1.3 $
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Mapper Version : spartan3 -- $Revision: 1.1.1.4 $
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Mapped Date : Wed Nov 15 08:50:16 2006
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Mapped Date : Thu Nov 16 20:11:36 2006
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Design Summary
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Design Summary
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--------------
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--------------
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Number of errors: 0
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Number of errors: 0
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Number of warnings: 13
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Number of warnings: 10
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Logic Utilization:
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Logic Utilization:
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Total Number Slice Registers: 745 out of 15,360 4%
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Total Number Slice Registers: 744 out of 15,360 4%
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Number used as Flip Flops: 657
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Number used as Flip Flops: 656
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Number used as Latches: 88
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Number used as Latches: 88
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Number of 4 input LUTs: 4,391 out of 15,360 28%
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Number of 4 input LUTs: 4,397 out of 15,360 28%
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Logic Distribution:
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Logic Distribution:
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Number of occupied Slices: 3,458 out of 7,680 45%
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Number of occupied Slices: 3,445 out of 7,680 44%
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Number of Slices containing only related logic: 3,458 out of 3,458 100%
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Number of Slices containing only related logic: 3,445 out of 3,445 100%
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Number of Slices containing unrelated logic: 0 out of 3,458 0%
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Number of Slices containing unrelated logic: 0 out of 3,445 0%
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*See NOTES below for an explanation of the effects of unrelated logic
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*See NOTES below for an explanation of the effects of unrelated logic
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Total Number 4 input LUTs: 6,313 out of 15,360 41%
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Total Number 4 input LUTs: 6,317 out of 15,360 41%
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Number used as logic: 4,391
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Number used as logic: 4,397
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Number used as a route-thru: 242
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Number used as a route-thru: 240
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Number used for Dual Port RAMs: 1,680
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Number used for Dual Port RAMs: 1,680
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(Two LUTs used per Dual Port RAM)
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(Two LUTs used per Dual Port RAM)
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Number of bonded IOBs: 54 out of 173 31%
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Number of bonded IOBs: 54 out of 173 31%
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IOB Flip Flops: 11
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IOB Flip Flops: 11
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Number of Block RAMs: 4 out of 24 16%
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Number of Block RAMs: 4 out of 24 16%
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Number of MULT18X18s: 2 out of 24 8%
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Number of MULT18X18s: 2 out of 24 8%
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Number of GCLKs: 2 out of 8 25%
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Number of GCLKs: 2 out of 8 25%
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Total equivalent gate count for design: 415,496
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Total equivalent gate count for design: 415,467
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Additional JTAG gate count for IOBs: 2,592
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Additional JTAG gate count for IOBs: 2,592
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Peak Memory Usage: 199 MB
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Peak Memory Usage: 199 MB
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NOTES:
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NOTES:
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| Line 96... |
Line 96... |
Pin CLR of cpu/readmem
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Pin CLR of cpu/readmem
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Pin CLR of cpu/inta
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Pin CLR of cpu/inta
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Pin CE of cpu/addr_0
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Pin CE of cpu/addr_0
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Pin CE of cpu/addr_1
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Pin CE of cpu/addr_1
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Pin CE of cpu/addr_2
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Pin CE of cpu/addr_2
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WARNING:Pack:266 - The function generator adm3a/display/chradr<5>35 failed to
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merge with F5 multiplexer adm3a/display/chradr<6>_f5_3. There is a conflict
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for the FXMUX. The design will exhibit suboptimal timing.
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WARNING:Pack:266 - The function generator cpu/_mux0003_SW1 failed to merge with
|
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F5 multiplexer cpu/_mux0003. There is a conflict for the FXMUX. The design
|
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will exhibit suboptimal timing.
|
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WARNING:Pack:266 - The function generator cpu/_mux0003_SW1 failed to merge with
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F5 multiplexer cpu/_mux00071_f5. There is a conflict for the FXMUX. The
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design will exhibit suboptimal timing.
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is
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sourced by a combinatorial pin. This is not good design practice. Use the CE
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sourced by a combinatorial pin. This is not good design practice. Use the CE
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pin to control the loading of data into the flip-flop.
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pin to control the loading of data into the flip-flop.
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
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