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https://opencores.org/ocsvn/cpu_lecture/cpu_lecture/trunk
[/] [cpu_lecture/] [trunk/] [src/] [opc_fetch.vhd] - Diff between revs 2 and 10
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| Rev 2 |
Rev 10 |
| Line 119... |
Line 119... |
-- 1001 1001 AAAA Abbb - SBIC
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-- 1001 1001 AAAA Abbb - SBIC
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-- 1001 1011 AAAA Abbb - SBIS
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-- 1001 1011 AAAA Abbb - SBIS
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-- 1111 110r rrrr 0bbb - SBRC
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-- 1111 110r rrrr 0bbb - SBRC
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-- 1111 111r rrrr 0bbb - SBRS
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-- 1111 111r rrrr 0bbb - SBRS
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--
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--
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L_WAIT <= '0' when (L_INVALIDATE = '1')
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L_WAIT <= '0' when ((L_INVALIDATE = '1') or (I_INTVEC(5) = '1'))
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else '0' when (I_INTVEC(5) = '1')
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else L_T0 when ((P_OPC(15 downto 9) = "1001000" ) -- LDS etc.
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else L_T0 when ((P_OPC(15 downto 9) = "1001000" ) -- LDS etc.
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or (P_OPC(15 downto 8) = "10010101") -- RET etc.
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or ((P_OPC(15 downto 8) = "10010101") -- RET etc.
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and (P_OPC(3 downto 0) /= "1010")) -- but not DEC
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or ((P_OPC(15 downto 10) = "100110") -- SBIC, SBIS
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or ((P_OPC(15 downto 10) = "100110") -- SBIC, SBIS
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and P_OPC(8) = '1')
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and (P_OPC(8) = '1'))
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or (P_OPC(15 downto 10) = "111111")) -- SBRC, SBRS
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or (P_OPC(15 downto 10) = "111111")) -- SBRC, SBRS
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else '0';
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else '0';
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L_INVALIDATE <= I_CLR or I_SKIP;
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L_INVALIDATE <= I_CLR or I_SKIP;
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