Line 1... |
Line 1... |
|
//////////////////////////////////////////////////////////////////
|
|
////
|
|
////
|
|
//// CRCAHB CORE BLOCK
|
|
////
|
|
////
|
|
////
|
|
//// This file is part of the APB to I2C project
|
|
////
|
|
//// http://www.opencores.org/cores/apbi2c/
|
|
////
|
|
////
|
|
////
|
|
//// Description
|
|
////
|
|
//// Implementation of APB IP core according to
|
|
////
|
|
//// crcahb IP core specification document.
|
|
////
|
|
////
|
|
////
|
|
//// To Do: Things are right here but always all block can suffer changes
|
|
////
|
|
////
|
|
////
|
|
////
|
|
////
|
|
//// Author(s): - Julio Cesar
|
|
////
|
|
/////////////////////////////////////////////////////////////////
|
|
////
|
|
////
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG
|
|
////
|
|
////
|
|
////
|
|
//// This source file may be used and distributed without
|
|
////
|
|
//// restriction provided that this copyright statement is not
|
|
////
|
|
//// removed from the file and that any derivative work contains
|
|
//// the original copyright notice and the associated disclaimer.
|
|
////
|
|
////
|
|
//// This source file is free software; you can redistribute it
|
|
////
|
|
//// and/or modify it under the terms of the GNU Lesser General
|
|
////
|
|
//// Public License as published by the Free Software Foundation;
|
|
//// either version 2.1 of the License, or (at your option) any
|
|
////
|
|
//// later version.
|
|
////
|
|
////
|
|
////
|
|
//// This source is distributed in the hope that it will be
|
|
////
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied
|
|
////
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
|
////
|
|
//// PURPOSE. See the GNU Lesser General Public License for more
|
|
//// details.
|
|
////
|
|
////
|
|
////
|
|
//// You should have received a copy of the GNU Lesser General
|
|
////
|
|
//// Public License along with this source; if not, download it
|
|
////
|
|
//// from http://www.opencores.org/lgpl.shtml
|
|
////
|
|
////
|
|
///////////////////////////////////////////////////////////////////
|
|
|
|
|
|
|
//This module implements the combinational logic for one iteration of CRC Calculation
|
//This module implements the combinational logic for one iteration of CRC Calculation
|
//If conected to shift register and after n clock cycles, this module realize CRC calculation
|
//If conected to shift register and after n clock cycles, this module realize CRC calculation
|
//for n bits of data.
|
//for n bits of data.
|
//If instantiated in serial form, this module realize the parallel CRC calculation
|
//If instantiated in serial form, this module realize the parallel CRC calculation
|
//for n bits of data.
|
//for n bits of data.
|