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?rev2line? |
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#-- Synplicity, Inc.
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#-- Version Synplify Pro 8.6.2
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#-- Project file /home/amb33/cryptopan/cryptopan.prj
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#-- Written on Thu Feb 15 11:59:26 2007
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#add_file options
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add_file -vhdl -lib work "rtl/dual_bram_256x8.vhd"
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add_file -vhdl -lib work "rtl/cryptopan_package.vhd"
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add_file -vhdl -lib work "rtl/sbox.vhd"
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add_file -vhdl -lib work "rtl/subbytesshiftrows.vhd"
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add_file -vhdl -lib work "rtl/mixcolumns.vhd"
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add_file -vhdl -lib work "rtl/round_unit.vhd"
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add_file -vhdl -lib work "rtl/aes_encrypt_unit.vhd"
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add_file -vhdl -lib work "rtl/cryptopan_unit.vhd"
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#implementation: "rev_1"
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impl -add rev_1 -type fpga
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#device options
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set_option -technology VIRTEX4
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set_option -part XC4VFX60
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set_option -package FF1152
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set_option -speed_grade -11
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#compilation/mapping options
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set_option -default_enum_encoding default
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set_option -symbolic_fsm_compiler 1
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set_option -resource_sharing 1
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set_option -use_fsm_explorer 0
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#map options
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set_option -frequency 250.000
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set_option -run_prop_extract 1
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set_option -fanout_limit 10000
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set_option -disable_io_insertion 0
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set_option -pipe 1
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set_option -update_models_cp 0
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set_option -verification_mode 0
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set_option -modular 0
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set_option -retiming 0
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set_option -no_sequential_opt 0
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set_option -fixgatedclocks 0
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#simulation options
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set_option -write_verilog 0
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set_option -write_vhdl 0
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#VIF options
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set_option -write_vif 1
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#automatic place and route (vendor) options
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set_option -write_apr_constraint 1
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#set result format/file last
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project -result_file "rev_1/cryptopan_unit.edf"
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#
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#implementation attributes
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set_option -vlog_std v2001
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set_option -project_relative_includes 1
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#par_1 attributes
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set_option -job par_1 -add par
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set_option -job par_1 -option run_backannotation 0
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impl -active "rev_1"
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