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[/] [csa/] [trunk/] [quartus10/] [csa_fpga.v] - Diff between revs 28 and 30

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Rev 28 Rev 30
Line 27... Line 27...
 
 
 
 
        wire usbclk = ifclk;
        wire usbclk = ifclk;
        wire ep6_havedata = flaga;
        wire ep6_havedata = flaga;
        wire ep2_haveroom = flagc;
        wire ep2_haveroom = flagc;
 
        wire ep8_havedata = flagb;
 
 
        assign bell = 1'h1;
        assign bell = 1'h1;
 
 
`define CNT_WIDTH 25
`define CNT_WIDTH 25
`define STA_WIDTH 4
`define STA_WIDTH 4
Line 56... Line 57...
        wire seg_clk = led_cnt[`CNT_WIDTH-16];
        wire seg_clk = led_cnt[`CNT_WIDTH-16];
        ledseg_cnt ledseg1(
        ledseg_cnt ledseg1(
                         .clk      (usbclk)
                         .clk      (usbclk)
                       , .rst      (rst)
                       , .rst      (rst)
                       , .scan     (seg_clk)
                       , .scan     (seg_clk)
                       , .data     (fd)
                       , .data     (usb_dat_in)
                       , .seg      (ledseg)
                       , .seg      (ledseg)
                       , .segd     (seg_d)
                       , .segd     (seg_d)
                        );
                        );
 
 
        ////////////////////////////////////////////////////////////////////////////////
        ////////////////////////////////////////////////////////////////////////////////
        // usb interface
        // usb interface
        ////////////////////////////////////////////////////////////////////////////////
        ////////////////////////////////////////////////////////////////////////////////
 
        assign slcs  =1'h0;
 
        assign pktend=1'h1;
 
 
 
`define EP2_W  2'h0
 
`define EP6_R  2'h1
 
`define EP8_R  2'h2
 
`define NO_ACT 2'h3
 
 
 
        reg [ 1:0] last_action;
 
        reg [15:0] usb_dat_out;
 
        reg [15:0] usb_dat_in;
 
 
 
        always @(posedge usbclk)
 
                if(ep6_havedata)
 
                begin
 
                        sloe<=1'h0;
 
                        fifoadr<=2'h2;
 
                        slrd<=1'h0;
 
                        slwr<=1'h1;
 
                        last_action<=`EP6_R;
 
                end
 
                else
 
                if(ep8_havedata)
 
                begin
 
                        sloe<=1'h0;
 
                        fifoadr<=2'h3;
 
                        slrd<=1'h0;
 
                        slwr<=1'h1;
 
                        last_action<=`EP8_R;
 
                end
 
                else
 
                if(ep2_haveroom)
 
                begin
 
                        // ouput data
 
                        sloe<=1'h1;
 
                        fifoadr<=2'h0;
 
                        slwr<=1'h0;
 
                        slrd<=1'h1;
 
                        last_action<=`EP2_W;
 
 
 
                end
 
                else
 
                begin
 
                        sloe<=1'h1;
 
                        fifoadr<=2'h0;
 
                        slwr<=1'h1;
 
                        slrd<=1'h1;
 
                        last_action<=`NO_ACT;
 
                end
 
 
 
        always @(posedge usbclk)
 
                if(last_action==`EP8_R )
 
                        usb_dat_in<=fd;
 
 
 
        assign fd=(sloe)?usb_dat_out:16'hzzzz;
 
 
        ////////////////////////////////////////////////////////////////////////////////
        ////////////////////////////////////////////////////////////////////////////////
        // csa decrypt module
        // csa decrypt module
        ////////////////////////////////////////////////////////////////////////////////
        ////////////////////////////////////////////////////////////////////////////////
        decrypt csa_decrypt(
        decrypt csa_decrypt(
                                 . clk            (ifclk)
                                 . clk            (usbclk)
                                ,. rst            (rst)
                                ,. rst            (rst)
                                ,. ck             (64'h0000000000000000)
                                ,. ck             (64'h0000000000000000)
                                ,. key_en         (1'h0)
                                ,. key_en         (1'h0)
                                ,. even_odd       (1'h0)
                                ,. even_odd       (1'h0)
                                ,. en             ()
                                ,. en             ()

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