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[/] [csa/] [trunk/] [rtl/] [group_decrypt.v] - Diff between revs 44 and 49
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Rev 49 |
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`include "../bench/timescale.v"
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`include "../bench/timescale.v"
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// this moduel do a decrypt group
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// this moduel do a decrypt group
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module group_decrypt(
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module group_decrypt(
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input clk
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input clk // clk
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, input rst
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, input rst // rst, high active
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, input en
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, input en // input enable
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, input dec
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, input init // the first packet
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, input init
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, input last // the last packet
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, input [ 8*8-1:0] ck
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, input [ 8*8-1:0] ck // ck
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, input [56*8-1:0] kk
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, input [56*8-1:0] kk // kk
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, input [ 8*8-1:0] group
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, input [ 8*8-1:0] group // packet
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, input [ 4-1:0] bytes
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, output valid // output vaild
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, output [ 8*8-1:0] ogroup // output packet
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, output valid
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, output [ 8*8-1:0] ogroup
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, output [ 4-1:0] obytes
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);
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);
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reg init_d;
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wire [8*8-1:0] stream;
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wire [8*8-1:0] stream;
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wire [8*8-1:0] ib;
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wire [8*8-1:0] block;
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reg [8*8-1:0] bco_d;
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reg [8*8-1:0] block_d;
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wire [8*8-1:0] bco;
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reg [8*8-1:0] init_d;
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reg en_d;
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reg [8*8-1:0] last_d;
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reg [8*8-1:0] last_dd;
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always @(posedge clk)
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reg [8*8-1:0] en_d;
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en_d<=en;
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reg [8*8-1:0] en_dd;
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always @(posedge clk)
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init_d<=init;
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always @(posedge clk)
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reg busy;
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if(en_d)
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wire [8*8-1:0] ib;
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bco_d<=bco;
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assign ib=(init_d)?group:group^stream;
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stream_cypher stream_cypher(
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stream_cypher stream_cypher(
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.clk (clk)
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.clk (clk)
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, .rst (rst)
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, .rst (rst)
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, .en (en)
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, .en (en)
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);
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);
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block_decypher block_decypher(
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block_decypher block_decypher(
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.kk (kk)
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.kk (kk)
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, .ib (ib)
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, .ib (ib)
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, .bd (bco)
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, .bd (block)
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);
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);
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assign ogroup=group^bco_d^stream;
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assign valid=en_d & ~init_d;
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always @(posedge clk)
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assign obytes=4'h8;
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if(en_d)
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block_d<=block;
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always @(posedge clk)
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if(en)
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init_d<=init;
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always @(posedge clk)
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last_dd<=last_d;
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always @(posedge clk)
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if(en)
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last_d<=last;
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always @(posedge clk)
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en_d<=en;
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always @(posedge clk)
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en_dd<=en_d;
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assign ogroup=(en_dd&last_dd)?block_d:ib^block_d;
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assign valid=((busy)&en) | (en_dd&last_dd);
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assign ib=(init)?group:group^stream;
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always @(posedge clk )
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if(rst)
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busy<=1'h0;
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else
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begin
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if(init_d)
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busy<=1'h1;
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if(last_d)
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busy<=1'h0;
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end
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endmodule
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endmodule
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