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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use work.protocol_pkg.all;
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--use work.decode_pkg.all;
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use work.timer_pkg.all;
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entity DS1821 is
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port
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(
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master_clk, master_rst : IN std_logic;
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clk : INOUT std_logic;
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tempValid : OUT std_logic;
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reset, read1, write1 : INOUT std_logic;
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DQ1 : INOUT std_logic;
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rddata1 : INOUT std_logic_vector(7 downto 0);
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wrdata1 : INOUT std_logic_vector(7 downto 0);
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ready1 : INOUT std_logic
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--useg : OUT std_logic_vector( 0 to 6 );
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--lseg : OUT std_logic_vector( 0 to 6 )
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);
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end entity;
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architecture DS1821Controller of DS1821 is
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component one_wire is
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port (
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clk, reset, read, write : IN std_logic;
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DQ : INOUT std_logic;
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rddata : INOUT std_logic_vector(7 downto 0);
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wrdata : IN std_logic_vector(7 downto 0);
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ready : INOUT std_logic);
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end component;
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--component seg_decode is --this component is only needed for debugging
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-- port(
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-- value : IN std_logic_vector (3 downto 0);
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-- output : OUT std_logic_vector (0 to 6));
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--end component;
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component clk_divider is
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port(
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clk : IN std_logic;
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oneus_plus : INOUT std_logic);
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end component;
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type states is (init, sendCommStatProg, sendCommStatVal, init1, sendConvTempComm, init2, sendReadTempComm, readTemp);
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signal state :states;
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signal next_state :states;
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begin
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temperaturemap1: one_wire port map(clk, reset, read1, write1, DQ1, rddata1, wrdata1, ready1);
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clkdivider: clk_divider port map(master_clk, clk); --clock divider to make this work with 25.175Mhz
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--usegdecode: seg_decode port map(rddata1(7 downto 4), useg); --seven seg decoder for debugging
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--lsegdecode: seg_decode port map(rddata1(3 downto 0), lseg); --seven seg decoder for debugging
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process ( clk, master_rst )
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begin
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if master_rst = '0' then
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wrdata1 <= wrdata1;
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write1 <= write1;
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read1 <= read1;
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tempValid <= '0';
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reset <= '1';
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next_state <= init;
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state <= init;
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elsif rising_edge( clk ) then
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state <= next_state;
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case state is
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when init =>
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write1 <= '0';
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read1 <= '0';
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reset <= '1';
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tempValid <= '0';
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next_state <= sendCommStatProg;
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when sendCommStatProg =>
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reset <= '0';
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if ready1 = '1' then
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wrdata1 <= "00001100"; --send 0Ch = Configure the register command
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write1 <= '1';
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next_state <= sendCommStatVal;
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end if;
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when sendCommStatVal =>
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write1 <= '0';
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if ready1 = '1' then
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wrdata1 <= "01000010"; --send 42h = Write this value into the register
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write1 <= '1';
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next_state <= init1;
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end if;
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when init1 =>
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write1 <= '0';
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read1 <= '0';
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if ready1 = '1' then
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reset <= '1';
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next_state <= sendConvTempComm;
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end if;
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when sendConvTempComm =>
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reset <= '0';
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--write1 <= '0';
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--tempValid <= '0';
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if ready1 = '1' AND reset <= '0' then
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wrdata1 <= "11101110"; --send EEh = Begin Conversions
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write1 <= '1';
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next_state <= init2;
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end if;
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when init2 =>
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if read1 = '1' then
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read1 <= '0';
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tempValid <= '0';
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end if;
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write1 <= '0';
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if ready1 = '1' then
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reset <= '1';
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tempValid <= '0';
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next_state <= sendReadTempComm;
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end if;
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when sendReadTempComm =>
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tempValid <= '1';
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reset <= '0';
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write1 <= '0';
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if ready1 = '1' AND reset <= '0' then
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tempValid <= '1';
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wrdata1 <= "10101010"; --send AAh = Read Temp Command
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write1 <= '1';
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next_state <= readTemp;
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end if;
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when readTemp => --starts reading the temperature
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write1 <= '0';
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tempValid <= '1';
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if ready1 = '1' then
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read1 <= '1';
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tempValid <= '0';
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next_state <= init2;
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end if;
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--when holdTemp => --For now I just hold the temp steady after one read
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-- read1 <= '0';
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-- if ready1 = '1' then
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-- tempValid <= '1';
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-- --ftemp <= rddata1 * "00001001";
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-- end if;
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-- next_state <= holdTemp;
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when OTHERS =>
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end case;
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end if;
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end process;
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end architecture;
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PACKAGE TEMPERATURE_PKG IS
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COMPONENT DS1821
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END COMPONENT;
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END TEMPERATURE_PKG;
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