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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_unsigned.all;
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entity one_wire is
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port (
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clk, reset, read, write : IN std_logic;
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DQ : INOUT std_logic;
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rddata : OUT std_logic_vector(7 downto 0);
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wrdata : IN std_logic_vector(7 downto 0);
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ready : INOUT std_logic
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);
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end entity one_wire;
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architecture structural of one_wire is
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signal iCount : integer range 0 to 500;
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signal iCntRst : bit;
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signal iD : std_logic;
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begin
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--This counter is used in the state machine to count micro seconds
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--it is assumed that the clock edges are coming in at 1uS intervals
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counter: process
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begin
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wait until (clk'event and clk = '0');
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if(iCntRst = '1') then
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iCount <= 0;
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else
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iCount <= iCount + 1;
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end if;
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end process counter;
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init_statemachine : block
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type states is (init1, init2, init3, rdy, begin_read, begin_write, rd_bit, finish_read, wr_bit);
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signal state : states;
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begin
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nxt_state_decoder: process(state, clk)
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variable next_state : states;
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variable iBits : integer range 0 to 8;
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begin
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if clk 'event and clk = '1' then
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case (state) is
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when INIT1 =>
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iCntRst <= '0';
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iD <= '0';
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ready <= '0';
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if (iCount = 500) then
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next_state := INIT2;
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iCntRst <= '1'; --stop the timer
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else
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next_state := INIT1;
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end if;
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when INIT2 =>
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iCntRst <= '0'; --start the timer
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iD <= '1';
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ready <= '0';
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if (iCount = 15) then
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next_state := INIT3;
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iCntRst <= '1'; --stop the timer
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else
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next_state := INIT2;
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end if;
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when INIT3 =>
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iCntRst <= '0'; --start the timer (not needed)
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ready <= '0';
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if (DQ = '0') then
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next_state := RDY;
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iCntRst <= '1'; --stop the timer (not needed)
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else
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next_state := INIT3;
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end if;
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when RDY =>
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iCntRst <= '0'; --start the timer
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iBits := 0;
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iD <= '1';
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if(iCount >= 240 and ready = '0') then
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ready <= '1';
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end if;
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if(Read = '1' and iCount >= 240) then
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ready <= '0';
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iCntRst <= '1'; --stop timer
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next_state := BEGIN_READ;
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elsif(Write = '1' and iCount >= 240) then
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ready <= '0';
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iCntRst <= '1'; --stop timer
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next_state := BEGIN_WRITE;
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else
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next_state := RDY;
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end if;
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when BEGIN_READ =>
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iCntRst <= '0'; --start timer
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iD <= '0';
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if (iCount = 2) then --this number used to be a 5
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iCntRst <= '1'; --stop timer
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next_state := RD_BIT;
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end if;
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when RD_BIT =>
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iD <= '1';
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iCntRst <= '0'; --start timer
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case ibits is
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when 0 =>
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rddata(0) <= DQ;
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when 1 =>
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rddata(1) <= DQ;
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when 2 =>
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rddata(2) <= DQ;
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when 3 =>
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rddata(3) <= DQ;
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when 4 =>
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rddata(4) <= DQ;
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when 5 =>
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rddata(5) <= DQ;
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when 6 =>
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rddata(6) <= DQ;
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when 7 =>
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rddata(7) <= DQ;
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when others =>
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end case;
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if(iCount >= 6) then
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next_state := FINISH_READ;
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end if;
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when FINISH_READ =>
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if(iBits <= 6 and iCount >= 55) then --this second number used to be 55
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iD <= '1';
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iBits := iBits + 1;
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iCntRst <= '1'; --stop timer
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next_state := BEGIN_READ;
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elsif(iBits = 7) then
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iCntRst <= '1'; -- stop timer
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next_state := RDY;
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end if;
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when BEGIN_WRITE =>
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iCntRst <= '0';
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if(iBits <= 7) then
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iD <= '0'; --start timer
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end if;
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if (iCount = 1) then
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iCntRst <= '1'; --stop timer
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next_state := WR_BIT;
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end if;
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when WR_BIT =>
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iCntRst <= '0';
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--The below code is what is being accomplished by the huge if elseif structure
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--if(data(iBits) = "001") then
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-- iD := '1';
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--end if;
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if(iBits = 0 and wrdata(0) = '1') then
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iD <= '1';
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elsif(iBIts = 0 and wrdata(0) = '0') then
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iD <= '0';
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elsif(iBits = 1 and wrdata(1) = '1') then
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iD <= '1';
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elsif(iBIts = 1 and wrdata(1) = '0') then
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iD <= '0';
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elsif(iBits = 2 and wrdata(2) = '1') then
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iD <= '1';
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elsif(iBIts = 2 and wrdata(2) = '0') then
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iD <= '0';
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elsif(iBits = 3 and wrdata(3) = '1') then
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iD <= '1';
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elsif(iBIts = 3 and wrdata(3) = '0') then
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iD <= '0';
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elsif(iBits = 4 and wrdata(4) = '1') then
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iD <= '1';
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elsif(iBIts = 4 and wrdata(4) = '0') then
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iD <= '0';
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elsif(iBits = 5 and wrdata(5) = '1') then
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iD <= '1';
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elsif(iBIts = 5 and wrdata(5) = '0') then
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iD <= '0';
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elsif(iBits = 6 and wrdata(6) = '1') then
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iD <= '1';
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elsif(iBIts = 6 and wrdata(6) = '0') then
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iD <= '0';
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elsif(iBits = 7 and wrdata(7) = '1') then
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iD <= '1';
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elsif(iBIts = 7 and wrdata(7) = '0') then
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iD <= '0';
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end if;
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if(iCount >= 60 and iBits <= 7) then
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iBits := iBits + 1;
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iD <= '1';
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iCntRst <= '1'; --stop timer
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next_state := BEGIN_WRITE;
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elsif(iBits = 8) then
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iD <= '1';
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iCntRst <= '1'; --stop timer
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next_state := RDY;
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end if;
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end case;
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state <= next_state;
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if(reset = '1') then
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state <= init1;
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end if;
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end if;
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end process nxt_state_decoder;
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end block init_statemachine;
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trictrl: process(iD)
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begin
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if( iD = '0' ) then
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DQ <= '0';
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else
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DQ <= 'Z';
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end if;
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end process trictrl;
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end architecture structural;
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PACKAGE PROTOCOL_PKG IS
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COMPONENT one_wire
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END COMPONENT;
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END PROTOCOL_PKG;
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