| Line 78... |
Line 78... |
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//`define __RMW_CYCLE__
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//`define __RMW_CYCLE__
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// muti-threading support:
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// muti-threading support:
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//
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//
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// Decreases clock performance by 20% (80MHz), but enables two contexts
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// Decreases clock performance by 20% (80MHz), but enables two or more
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// (threads) in the core. The threads work in symmetrical way, which means
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// contexts (threads) in the core. The threads work in symmetrical way,
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// that they will start with the same exactly core parameters (same initial
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// which means that they will start with the same exactly core parameters
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// PC, same initial SP, etc). The boot.s code is designed to handle this
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// (same initial PC, same initial SP, etc). The boot.s code is designed
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// difference and set each thread to different applications.
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// to handle this difference and set each thread to different
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// applications.
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// Notes:
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// Notes:
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// a) threading is currently supported only in the 3-stage pipeline version.
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// a) threading is currently supported only in the 3-stage pipeline version.
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// b) the old experimental "interrupt mode" was removed, which means that
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// b) the old experimental "interrupt mode" was removed, which means that
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// the multi-thread mode does not make anything "visible" other than
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// the multi-thread mode does not make anything "visible" other than
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// increment the gpio register.
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// increment the gpio register.
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// c) the threading in the non interrupt mode just shares the core 50%/50%,
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// c) the threading in the non-interrupt mode switches when the program flow
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// in a way that the single-thread performance is reduced.
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// changes, i.e. every jal instruction. When the core is idle, it is
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// probably in a jal loop.
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//`define __THREADING__
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//`define __THREADING__
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// number of threads: between 2 and n. Of course, it requires more and
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// more FPGA space in order to implement it, depending of the FPGA technology.
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`define NTHREADS 4
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// performance measurement:
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// performance measurement:
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//
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//
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// The performance measurement can be done in the simulation level by
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// The performance measurement can be done in the simulation level by
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// eabling the __PERFMETER__ define, in order to check how the clock cycles
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// eabling the __PERFMETER__ define, in order to check how the clock cycles
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// are used in the core. The report is displayed when the FINISH_REQ signal
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// are used in the core. The report is displayed when the FINISH_REQ signal
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| Line 164... |
Line 171... |
// .data.
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// .data.
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`define __RESETPC__ 32'd0
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`define __RESETPC__ 32'd0
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`define __RESETSP__ 32'd8192
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`define __RESETSP__ 32'd8192
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// UART queue:
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//
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// Optional RX/TX queue for communication oriented applications. The concept
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// foreseen 256 bytes for TX and RX, in a way that frames up to 128 bytes can
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// be easily exchanged via UART.
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//`define __UARTQUEUE__
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// board definition:
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// board definition:
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//
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//
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// The board is automatically defined in the xst/xise files via Makefile or
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// The board is automatically defined in the xst/xise files via Makefile or
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// ISE. Case it is not the case, please define you board name here:
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// ISE. Case it is not the case, please define you board name here:
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| Line 255... |
Line 270... |
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`ifdef ALIEXPRESS_HPC40GBE_K420
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`ifdef ALIEXPRESS_HPC40GBE_K420
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`define BOARD_ID 8
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`define BOARD_ID 8
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//`define BOARD_CK 200000000
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//`define BOARD_CK 200000000
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`define BOARD_CK_REF 100000000
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`define BOARD_CK_REF 100000000
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`define BOARD_CK_MUL 11
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`define BOARD_CK_MUL 12
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`define BOARD_CK_DIV 5
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`define BOARD_CK_DIV 5
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`define XILINX7CLK 1
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`define XILINX7CLK 1
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`define INVRES 1
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`define INVRES 1
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`endif
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`endif
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| Line 271... |
Line 286... |
`define XILINX7CLK 1
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`define XILINX7CLK 1
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`define VIVADO 1
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`define VIVADO 1
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`define INVRES 1
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`define INVRES 1
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`endif
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`endif
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`ifdef ALIEXPRESS_HPC40GBE_XKCU040
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`define BOARD_ID 10
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//`define BOARD_CK 200000000
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`define BOARD_CK_REF 100000000
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`define BOARD_CK_MUL 8 // x8/2 = 400MHZ (overclock!)
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`define BOARD_CK_DIV 2 // vivado reco. = 250MHz
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`define XILINX7CLK 1
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`define INVRES 1
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`endif
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`ifndef BOARD_ID
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`ifndef BOARD_ID
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`define BOARD_ID 0
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`define BOARD_ID 0
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`define BOARD_CK 100000000
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`define BOARD_CK 100000000
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`endif
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`endif
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`ifdef BOARD_CK_REF
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`ifdef BOARD_CK_REF
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`define BOARD_CK (`BOARD_CK_REF * `BOARD_CK_MUL / `BOARD_CK_DIV)
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`define BOARD_CK (`BOARD_CK_REF * `BOARD_CK_MUL / `BOARD_CK_DIV)
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`endif
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`endif
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// the 3-stage pipeline is required when the threading mode is enabled,
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// also, we need a non-null number of threads (default 2)
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`ifdef __THREADING__
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`ifndef __3STAGE__
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`define __3STAGE__
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`endif
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`ifndef NTHREADS
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`define NTHREADS 2
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`endif
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`endif
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// darkuart baudrate automtically calculated according to board clock:
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// darkuart baudrate automtically calculated according to board clock:
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`ifndef __UARTSPEED__
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`ifndef __UARTSPEED__
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`define __UARTSPEED__ 115200
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`define __UARTSPEED__ 115200
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`endif
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`endif
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