| Line 64... |
Line 64... |
// (instruction per clock = 1). of course, read operations require 1
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// (instruction per clock = 1). of course, read operations require 1
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// wait-state, which means sometimes the read performance is reduced.
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// wait-state, which means sometimes the read performance is reduced.
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`define __3STAGE__
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`define __3STAGE__
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// read-modify-write cycle:
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//
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// Generate RMW cycles when writing in the memory. This option basically
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// makes the read and write cycle symmetric and may work better in the cases
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// when the 32-bit memory does not support separate write enables for
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// separate 16-bit and 8-bit words. Typically, the RMW cycle results in a
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// decrease of 5% in the performance (not the clock, but the instruction
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// pipeline eficiency) due to memory wait-states.
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// Additional note: the RMW cycle is required for -O3 compilation!
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//`define __RMW_CYCLE__
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// muti-threading support:
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// muti-threading support:
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//
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//
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// Decreases clock performance by 10% (90MHz), but enables two contexts
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// Decreases clock performance by 20% (80MHz), but enables two contexts
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// (threads) in the core. They start in the same code, but the "interrupt"
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// (threads) in the core. The threads work in symmetrical way, which means
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// handling is locked in a separate loop and the conext switch is always
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// that they will start with the same exactly core parameters (same initial
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// delayed until the next pipeline flush, in order to decrease the
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// PC, same initial SP, etc). The boot.s code is designed to handle this
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// performance impact. Note: threading is currently supported only in the
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// difference and set each thread to different applications.
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// 3-stage pipeline version.
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// Notes:
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// a) threading is currently supported only in the 3-stage pipeline version.
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// b) the old experimental "interrupt mode" was removed, which means that
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// the multi-thread mode does not make anything "visible" other than
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// increment the gpio register.
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// c) the threading in the non interrupt mode just shares the core 50%/50%,
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// in a way that the single-thread performance is reduced.
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//`define __THREADING__
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//`define __THREADING__
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// performance measurement:
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// performance measurement:
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//
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//
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// The performance measurement can be done in the simulation level by
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// The performance measurement can be done in the simulation level by
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// eabling the __PERFMETER__ define, in order to check how the clock cycles
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// eabling the __PERFMETER__ define, in order to check how the clock cycles
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// are used in the core. The value defines how many clocks are computed
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// are used in the core. The report is displayed when the FINISH_REQ signal
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// before print the result.
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// is actived by the UART.
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//`define __PERFMETER__ 70000
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`define __PERFMETER__
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// mac instruction:
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// mac instruction:
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//
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//
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// The mac instruction is similar to other register to register
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// The mac instruction is similar to other register to register
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// instructions, but with a different opcode 7'h1111111. the format is mac
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// instructions, but with a different opcode 7'h1111111. the format is mac
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| Line 104... |
Line 122... |
// minimal in typical applications with modern 5 or 6 input LUT based FPGAs,
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// minimal in typical applications with modern 5 or 6 input LUT based FPGAs,
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// but the RV32E is better with old 4 input LUT based FPGAs.
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// but the RV32E is better with old 4 input LUT based FPGAs.
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`define __RV32E__
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`define __RV32E__
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// initial PC and SP
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//
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// it is possible program the initial PC and SP. Typically, the PC is set
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// to address 0, representing the start of ROM memory and the SP is set to
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// the final of RAM memory. In the linker, the start of ROM memory matches
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// with the .text area, which is defined in the boot.c code and the start of
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// RAM memory matches with the .data and other volatile data, in a way that
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// the stack can be positioned in the top of RAM and does not match with the
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// .data.
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`define __HARVARD__
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// full harvard architecture:
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// full harvard architecture:
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//
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//
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// When defined, enforses that the instruction and data buses are connected
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// When defined, enforses that the instruction and data buses are connected
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// to fully separate memory banks. Although the darkriscv always use
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// to fully separate memory banks. Although the darkriscv always use
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// harvard architecture in the core, with separate instruction and data
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// harvard architecture in the core, with separate instruction and data
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| Line 130... |
Line 136... |
// possible connect two separate buses in a single memory bank. the main
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// possible connect two separate buses in a single memory bank. the main
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// advantage of a single memory bank is that the .text and .data areas can
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// advantage of a single memory bank is that the .text and .data areas can
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// be better allocated, but in this case is not possible protect the .text
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// be better allocated, but in this case is not possible protect the .text
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// area as in the case of separate memory banks.
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// area as in the case of separate memory banks.
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`define __FLEXBUZZ__
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//`define __HARVARD__
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// flexbuzz interface (experimental):
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// flexbuzz interface (experimental):
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//
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//
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// A new data bus interface similar to a well known c*ldfire bus interface, in
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// A new data bus interface similar to a well known c*ldfire bus interface, in
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// a way that part of the bus routing is moved to the core, in a way that
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// a way that part of the bus routing is moved to the core, in a way that
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| Line 143... |
Line 149... |
// in the bus interface dinamically). Similarly to the standard 32-bit interface,
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// in the bus interface dinamically). Similarly to the standard 32-bit interface,
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// the external logic must detect the RD/WR operation quick enough and assert HLT
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// the external logic must detect the RD/WR operation quick enough and assert HLT
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// in order to insert wait-states and perform the required multiplexing to fit
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// in order to insert wait-states and perform the required multiplexing to fit
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// the DLEN operand size in the data bus width available.
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// the DLEN operand size in the data bus width available.
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`define __FLEXBUZZ__
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// initial PC and SP
|
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//
|
|
// it is possible program the initial PC and SP. Typically, the PC is set
|
|
// to address 0, representing the start of ROM memory and the SP is set to
|
|
// the final of RAM memory. In the linker, the start of ROM memory matches
|
|
// with the .text area, which is defined in the boot.c code and the start of
|
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// RAM memory matches with the .data and other volatile data, in a way that
|
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// the stack can be positioned in the top of RAM and does not match with the
|
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// .data.
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`define __RESETPC__ 32'd0
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`define __RESETPC__ 32'd0
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`define __RESETSP__ 32'd8192
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`define __RESETSP__ 32'd8192
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// board definition:
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// board definition:
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//
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//
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