| Line 60... |
Line 60... |
(
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(
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input CLK, // clock
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input CLK, // clock
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input RES, // reset
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input RES, // reset
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input HLT, // halt
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input HLT, // halt
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`ifdef __THREADING__
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//`ifdef __THREADING__
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input IREQ, // irq req
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// input IREQ, // irq req
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`endif
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//`endif
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input [31:0] IDATA, // instruction data bus
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input [31:0] IDATA, // instruction data bus
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output [31:0] IADDR, // instruction addr bus
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output [31:0] IADDR, // instruction addr bus
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input [31:0] DATAI, // data bus (input)
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input [31:0] DATAI, // data bus (input)
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| Line 80... |
Line 80... |
output [ 3:0] BE, // byte enable
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output [ 3:0] BE, // byte enable
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output WR, // write enable
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output WR, // write enable
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output RD, // read enable
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output RD, // read enable
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`endif
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`endif
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`ifdef SIMULATION
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input FINISH_REQ,
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`endif
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output [3:0] DEBUG // old-school osciloscope based debug! :)
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output [3:0] DEBUG // old-school osciloscope based debug! :)
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);
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);
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// dummy 32-bit words w/ all-0s and all-1s:
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// dummy 32-bit words w/ all-0s and all-1s:
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wire [31:0] ALL0 = 0;
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wire [31:0] ALL0 = 0;
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wire [31:0] ALL1 = -1;
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wire [31:0] ALL1 = -1;
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`ifdef __THREADING__
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`ifdef __THREADING__
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reg XMODE = 0; // 0 = user, 1 = exception
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reg XMODE = 0; // thread ptr
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`endif
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`endif
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// pre-decode: IDATA is break apart as described in the RV32I specification
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// pre-decode: IDATA is break apart as described in the RV32I specification
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reg [31:0] XIDATA;
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reg [31:0] XIDATA;
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| Line 338... |
Line 341... |
//0);
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//0);
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wire JREQ = (JAL||JALR||BMUX);
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wire JREQ = (JAL||JALR||BMUX);
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wire [31:0] JVAL = JALR ? DADDR : PC+SIMM; // SIMM + (JALR ? U1REG : PC);
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wire [31:0] JVAL = JALR ? DADDR : PC+SIMM; // SIMM + (JALR ? U1REG : PC);
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`ifdef SIMULATION
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`ifdef __PERFMETER__
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`ifdef __PERFMETER__
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integer clocks=0, user=0, super=0, halt=0, flush=0;
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integer clocks=0, thread0=0, thread1=0, load=0, store=0, flush=0, halt=0;
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always@(posedge CLK)
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always@(posedge CLK)
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begin
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begin
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if(!XRES)
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if(!XRES)
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begin
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begin
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clocks = clocks+1;
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clocks = clocks+1;
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if(HLT)
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begin
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if(SCC) store = store+1;
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else if(LCC) load = load +1;
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else halt = halt +1;
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end
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else
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begin
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if(FLUSH)
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begin
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flush=flush+1;
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end
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else
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begin
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`ifdef __THREADING__
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`ifdef __THREADING__
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if(XMODE==0 && !HLT && !FLUSH) user = user +1;
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if(XMODE==0) thread0 = thread0+1;
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if(XMODE==1 && !HLT && !FLUSH) super = super+1;
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if(XMODE==1) thread1 = thread1+1;
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`else
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`else
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if(!HLT && !FLUSH) user = user +1;
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thread0 = thread0 +1;
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`endif
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`endif
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end
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end
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if(HLT) halt=halt+1;
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if(FINISH_REQ)
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if(FLUSH) flush=flush+1;
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if(clocks && clocks%`__PERFMETER__==0)
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begin
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begin
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$display("%d clocks: %0d%% user, %0d%% super, %0d%% ws, %0d%% flush",
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$display("****************************************************************************");
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clocks,
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$display("DarkRISCV Pipeline Report:");
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100*user/clocks,
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$display("core0 clocks: %0d",clocks);
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100*super/clocks,
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100*halt/clocks,
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$display("core0 running: %0d%% (%0d%% thread0, %0d%% thread1)",
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100*flush/clocks);
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100.0*(thread0+thread1)/clocks,
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100.0*thread0/clocks,
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100.0*thread1/clocks);
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$display("core0 halted: %0d%% (%0d%% load, %0d%% store, %0d%% busy)",
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100.0*(load+store)/clocks,
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100.0*load/clocks,
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100.0*store/clocks,
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100.0*halt/clocks);
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$display("core0 stalled: %0d%%",100.0*flush/clocks);
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$display("****************************************************************************");
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$finish();
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end
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end
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end
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end
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end
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end
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`else
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$finish();
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`endif
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`endif
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`endif
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always@(posedge CLK)
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always@(posedge CLK)
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begin
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begin
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RESMODE <= RES ? -1 : RESMODE ? RESMODE-1 : 0;
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RESMODE <= RES ? -1 : RESMODE ? RESMODE-1 : 0;
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| Line 434... |
Line 466... |
NXPC2[RES ? RESMODE[0] : XMODE] <= XRES ? `__RESETPC__ : HLT ? NXPC2[XMODE] : // reset and halt
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NXPC2[RES ? RESMODE[0] : XMODE] <= XRES ? `__RESETPC__ : HLT ? NXPC2[XMODE] : // reset and halt
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JREQ ? JVAL : // jmp/bra
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JREQ ? JVAL : // jmp/bra
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NXPC2[XMODE]+4; // normal flow
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NXPC2[XMODE]+4; // normal flow
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XMODE <= XRES ? 0 : HLT ? XMODE : // reset and halt
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XMODE <= XRES ? 0 : HLT ? XMODE : // reset and halt
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XMODE==0&& IREQ&&(JAL||JALR||BMUX) ? 1 : // wait pipeflush to switch to irq
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XMODE==0/*&& IREQ*/&&(JAL||JALR||BMUX) ? 1 : // wait pipeflush to switch to irq
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XMODE==1&&!IREQ&&(JAL||JALR||BMUX) ? 0 : XMODE; // wait pipeflush to return from irq
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XMODE==1/*&&!IREQ*/&&(JAL||JALR||BMUX) ? 0 : XMODE; // wait pipeflush to return from irq
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`else
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`else
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NXPC <= /*XRES ? `__RESETPC__ :*/ HLT ? NXPC : NXPC2;
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NXPC <= /*XRES ? `__RESETPC__ :*/ HLT ? NXPC : NXPC2;
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NXPC2 <= XRES ? `__RESETPC__ : HLT ? NXPC2 : // reset and halt
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NXPC2 <= XRES ? `__RESETPC__ : HLT ? NXPC2 : // reset and halt
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