| Line 508... |
Line 508... |
// for single phase clock: 1 wait state in read op always required!
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// for single phase clock: 1 wait state in read op always required!
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reg [1:0] DACK = 0;
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reg [1:0] DACK = 0;
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wire WHIT = 1;
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wire WHIT = 1;
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wire DHIT = !((RD||WR) && DACK!=1); // the WR operatio does not need ws. in this config.
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wire DHIT = !((RD
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`ifdef __RMW_CYCLE__
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||WR // worst code ever! but it is 3:12am...
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`endif
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) && DACK!=1); // the WR operatio does not need ws. in this config.
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always@(posedge CLK) // stage #1.0
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always@(posedge CLK) // stage #1.0
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begin
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begin
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DACK <= RES ? 0 : DACK ? DACK-1 : (RD||WR) ? 1 : 0; // wait-states
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DACK <= RES ? 0 : DACK ? DACK-1 : (RD
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`ifdef __RMW_CYCLE__
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||WR // 2nd worst code ever!
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`endif
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) ? 1 : 0; // wait-states
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end
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end
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`else
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`else
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// for dual phase clock: 0 wait state
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// for dual phase clock: 0 wait state
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| Line 542... |
Line 550... |
//individual byte/word/long selection, thanks to HYF!
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//individual byte/word/long selection, thanks to HYF!
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always@(posedge CLK)
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always@(posedge CLK)
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begin
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begin
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`ifdef __3STAGE__
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`ifdef __RMW_CYCLE__
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// read-modify-write operation w/ 1 wait-state:
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// read-modify-write operation w/ 1 wait-state:
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if(!HLT&&WR&&DADDR[31]==0/*&&DADDR[12]==1*/)
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if(!HLT&&WR&&DADDR[31]==0/*&&DADDR[12]==1*/)
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begin
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begin
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| Line 564... |
Line 572... |
end
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end
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`else
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`else
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// write-only operation w/ 0 wait-states:
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// write-only operation w/ 0 wait-states:
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`ifdef __HARVARD__
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`ifdef __HARVARD__
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if(WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[3]) RAM[DADDR[11:2]][3 * 8 + 7: 3 * 8] <= DATAO[3 * 8 + 7: 3 * 8];
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if(!HLT&&WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[3]) RAM[DADDR[11:2]][3 * 8 + 7: 3 * 8] <= DATAO[3 * 8 + 7: 3 * 8];
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if(WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[2]) RAM[DADDR[11:2]][2 * 8 + 7: 2 * 8] <= DATAO[2 * 8 + 7: 2 * 8];
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if(!HLT&&WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[2]) RAM[DADDR[11:2]][2 * 8 + 7: 2 * 8] <= DATAO[2 * 8 + 7: 2 * 8];
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if(WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[1]) RAM[DADDR[11:2]][1 * 8 + 7: 1 * 8] <= DATAO[1 * 8 + 7: 1 * 8];
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if(!HLT&&WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[1]) RAM[DADDR[11:2]][1 * 8 + 7: 1 * 8] <= DATAO[1 * 8 + 7: 1 * 8];
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if(WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[0]) RAM[DADDR[11:2]][0 * 8 + 7: 0 * 8] <= DATAO[0 * 8 + 7: 0 * 8];
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if(!HLT&&WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[0]) RAM[DADDR[11:2]][0 * 8 + 7: 0 * 8] <= DATAO[0 * 8 + 7: 0 * 8];
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`else
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`else
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if(WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[3]) MEM[DADDR[12:2]][3 * 8 + 7: 3 * 8] <= DATAO[3 * 8 + 7: 3 * 8];
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if(!HLT&&WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[3]) MEM[DADDR[12:2]][3 * 8 + 7: 3 * 8] <= DATAO[3 * 8 + 7: 3 * 8];
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if(WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[2]) MEM[DADDR[12:2]][2 * 8 + 7: 2 * 8] <= DATAO[2 * 8 + 7: 2 * 8];
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if(!HLT&&WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[2]) MEM[DADDR[12:2]][2 * 8 + 7: 2 * 8] <= DATAO[2 * 8 + 7: 2 * 8];
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if(WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[1]) MEM[DADDR[12:2]][1 * 8 + 7: 1 * 8] <= DATAO[1 * 8 + 7: 1 * 8];
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if(!HLT&&WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[1]) MEM[DADDR[12:2]][1 * 8 + 7: 1 * 8] <= DATAO[1 * 8 + 7: 1 * 8];
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if(WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[0]) MEM[DADDR[12:2]][0 * 8 + 7: 0 * 8] <= DATAO[0 * 8 + 7: 0 * 8];
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if(!HLT&&WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[0]) MEM[DADDR[12:2]][0 * 8 + 7: 0 * 8] <= DATAO[0 * 8 + 7: 0 * 8];
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`endif
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`endif
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`endif
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`endif
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IOMUXFF <= IOMUX[DADDR[3:2]]; // read w/ 2 wait-states
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IOMUXFF <= IOMUX[DADDR[3:2]]; // read w/ 2 wait-states
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end
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end
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| Line 685... |
Line 693... |
.DATAI(DATAO),
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.DATAI(DATAO),
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.DATAO(IOMUX[1]),
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.DATAO(IOMUX[1]),
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//.IRQ(BOARD_IRQ[1]),
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//.IRQ(BOARD_IRQ[1]),
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.RXD(UART_RXD),
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.RXD(UART_RXD),
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.TXD(UART_TXD),
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.TXD(UART_TXD),
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`ifdef SIMULATION
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.FINISH_REQ(FINISH_REQ),
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`endif
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.DEBUG(UDEBUG)
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.DEBUG(UDEBUG)
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);
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);
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// darkriscv
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// darkriscv
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| Line 706... |
Line 717... |
`else
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`else
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.CLK(!CLK),
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.CLK(!CLK),
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`endif
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`endif
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.RES(RES),
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.RES(RES),
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.HLT(HLT),
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.HLT(HLT),
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`ifdef __THREADING__
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//`ifdef __THREADING__
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.IREQ(|(IREQ^IACK)),
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// .IREQ(|(IREQ^IACK)),
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`endif
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//`endif
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.IDATA(IDATA),
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.IDATA(IDATA),
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.IADDR(IADDR),
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.IADDR(IADDR),
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.DADDR(DADDR),
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.DADDR(DADDR),
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|
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`ifdef __FLEXBUZZ__
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`ifdef __FLEXBUZZ__
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| Line 726... |
Line 737... |
.BE(BE),
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.BE(BE),
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.WR(WR),
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.WR(WR),
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.RD(RD),
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.RD(RD),
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`endif
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`endif
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`ifdef SIMULATION
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.FINISH_REQ(FINISH_REQ),
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`endif
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.DEBUG(KDEBUG)
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.DEBUG(KDEBUG)
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);
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);
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`ifdef __ICARUS__
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`ifdef __ICARUS__
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initial
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initial
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