URL
https://opencores.org/ocsvn/darkriscv/darkriscv/trunk
[/] [darkriscv/] [trunk/] [rtl/] [darkuart.v] - Diff between revs 2 and 4
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 2 |
Rev 4 |
| Line 87... |
Line 87... |
output IRQ, // interrupt req
|
output IRQ, // interrupt req
|
|
|
input RXD, // UART recv line
|
input RXD, // UART recv line
|
output TXD, // UART xmit line
|
output TXD, // UART xmit line
|
|
|
|
`ifdef SIMULATION
|
|
output reg FINISH_REQ = 0,
|
|
`endif
|
|
|
output [3:0] DEBUG // osc debug
|
output [3:0] DEBUG // osc debug
|
);
|
);
|
|
|
reg [15:0] UART_TIMER = `__BAUD__; // baud rate from config.vh
|
reg [15:0] UART_TIMER = `__BAUD__; // baud rate from config.vh
|
reg UART_IREQ = 0; // UART interrupt req
|
reg UART_IREQ = 0; // UART interrupt req
|
| Line 138... |
Line 142... |
$stop();
|
$stop();
|
end
|
end
|
|
|
if(DATAI[15:8]==">") // prompt '>'
|
if(DATAI[15:8]==">") // prompt '>'
|
begin
|
begin
|
$display(" no UART input, finishing simulation...");
|
$display(" no UART input, end simulation request...");
|
$finish();
|
FINISH_REQ <= 1;
|
end
|
end
|
`else
|
`else
|
UART_XREQ <= !UART_XACK; // activate UART!
|
UART_XREQ <= !UART_XACK; // activate UART!
|
`endif
|
`endif
|
end
|
end
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.