| Line 64... |
Line 64... |
`define UART_STATE_STOP 0
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`define UART_STATE_STOP 0
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`define UART_STATE_ACK 1
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`define UART_STATE_ACK 1
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// UART registers
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// UART registers
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//
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//
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// 0: status register ro, 1 = xmit busy, 2 = recv busy
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// 0: status register ro, 1 = xmit busy, 2 = recv bfusy
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// 1: buffer register rw, w = xmit fifo, r = recv fifo
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// 1: buffer register rw, w = xmit fifo, r = recv fifo
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// 2: baud rate msb rw (not used)
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// 2: baud rate msb rw (not used)
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// 3: baud rate lsb rw (not used)
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// 3: baud rate lsb rw (not used)
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module darkuart
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module darkuart
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| Line 98... |
Line 98... |
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reg [15:0] UART_TIMER = `__BAUD__; // baud rate from config.vh
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reg [15:0] UART_TIMER = `__BAUD__; // baud rate from config.vh
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reg UART_IREQ = 0; // UART interrupt req
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reg UART_IREQ = 0; // UART interrupt req
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reg UART_IACK = 0; // UART interrupt ack
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reg UART_IACK = 0; // UART interrupt ack
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`ifdef __UARTQUEUE__
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reg [ 7:0] UART_XFIFO [0:255]; // UART TX FIFO
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wire [7:0] UART_XTMP; // UART TX FIFO
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reg [ 8:0] UART_XREQ = 0; // xmit request (core side)
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reg [ 8:0] UART_XACK = 0; // xmit ack (uart side)
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`else
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reg [ 7:0] UART_XFIFO = 0; // UART TX FIFO
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reg [ 7:0] UART_XFIFO = 0; // UART TX FIFO
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reg UART_XREQ = 0; // xmit request (core side)
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reg UART_XREQ = 0; // xmit request (core side)
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reg UART_XACK = 0; // xmit ack (uart side)
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reg UART_XACK = 0; // xmit ack (uart side)
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`endif
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reg [15:0] UART_XBAUD = 0; // baud rate counter
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reg [15:0] UART_XBAUD = 0; // baud rate counter
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reg [ 3:0] UART_XSTATE= 0; // idle state
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reg [ 3:0] UART_XSTATE= 0; // idle state
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`ifdef __UARTQUEUE__
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reg [ 7:0] UART_RFIFO [0:255]; // UART RX FIFO
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reg [ 7:0] UART_RTMP = 0; // UART RX FIFO
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reg [ 8:0] UART_RREQ = 0; // request (uart side)
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reg [ 8:0] UART_RACK = 0; // ack (core side)
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`else
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reg [ 7:0] UART_RFIFO = 0; // UART RX FIFO
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reg [ 7:0] UART_RFIFO = 0; // UART RX FIFO
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reg UART_RREQ = 0; // request (uart side)
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reg UART_RREQ = 0; // request (uart side)
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reg UART_RACK = 0; // ack (core side)
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reg UART_RACK = 0; // ack (core side)
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`endif
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reg [15:0] UART_RBAUD = 0; // baud rate counter
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reg [15:0] UART_RBAUD = 0; // baud rate counter
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reg [ 3:0] UART_RSTATE= 0; // idle state
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reg [ 3:0] UART_RSTATE= 0; // idle state
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reg [2:0] UART_RXDFF = -1;
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reg [2:0] UART_RXDFF = -1;
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wire [7:0] UART_STATE = { 6'd0, UART_RREQ^UART_RACK, UART_XREQ^UART_XACK };
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`ifdef __UARTQUEUE__
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wire [7:0] UART_STATE = { 6'd0, UART_RREQ!=UART_RACK, UART_XREQ==(UART_XACK^9'h100) };
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integer i;
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initial
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for(i=0;i!=256;i=i+1)
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begin
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UART_RFIFO[i] = 0;
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UART_XFIFO[i] = 0;
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end
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`else
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wire [7:0] UART_STATE = { 6'd0, UART_RREQ!=UART_RACK, UART_XREQ!=UART_XACK };
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`endif
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reg [7:0] UART_STATEFF = 0;
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reg [7:0] UART_STATEFF = 0;
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// bus interface
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// bus interface
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reg [31:0] DATAOFF = 0;
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reg [31:0] DATAOFF = 0;
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| Line 126... |
Line 152... |
begin
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begin
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if(WR)
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if(WR)
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begin
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begin
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if(BE[1])
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if(BE[1])
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begin
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begin
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UART_XFIFO <= DATAI[15:8];
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`ifdef SIMULATION
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`ifdef SIMULATION
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// print the UART output to console! :)
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// print the UART output to console! :)
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if(DATAI[15:8]!=13) // remove the '\r'
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if(DATAI[15:8]!=13) // remove the '\r'
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begin
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begin
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$write("%c",DATAI[15:8]);
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$write("%c",DATAI[15:8]);
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| Line 146... |
Line 172... |
begin
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begin
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$display(" no UART input, end simulation request...");
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$display(" no UART input, end simulation request...");
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FINISH_REQ <= 1;
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FINISH_REQ <= 1;
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end
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end
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`else
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`else
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`ifdef __UARTQUEUE__
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if(UART_XREQ!=(UART_XACK^9'h100))
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begin
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UART_XFIFO[UART_XREQ[7:0]] <= DATAI[15:8];
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UART_XREQ <= UART_XREQ+1;
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end
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`else
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UART_XFIFO <= DATAI[15:8];
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UART_XREQ <= !UART_XACK; // activate UART!
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UART_XREQ <= !UART_XACK; // activate UART!
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`endif
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`endif
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`endif
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end
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end
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//if(BE[2]) UART_TIMER[ 7:0] <= DATAI[23:16];
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//if(BE[2]) UART_TIMER[ 7:0] <= DATAI[23:16];
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//if(BE[3]) UART_TIMER[15:8] <= DATAI[31:24];
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//if(BE[3]) UART_TIMER[15:8] <= DATAI[31:24];
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end
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end
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| Line 161... |
Line 196... |
UART_STATEFF <= UART_STATE;
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UART_STATEFF <= UART_STATE;
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end
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end
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else
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else
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if(RD)
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if(RD)
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begin
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begin
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`ifdef __UARTQUEUE__
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if(BE[1]) UART_RACK <= UART_RACK!=UART_RREQ?UART_RACK+1:UART_RACK; // fifo ready
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`else
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if(BE[1]) UART_RACK <= UART_RREQ; // fifo ready
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if(BE[1]) UART_RACK <= UART_RREQ; // fifo ready
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`endif
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if(BE[0]) UART_STATEFF <= UART_STATE; // state update, clear irq
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if(BE[0]) UART_STATEFF <= UART_STATE; // state update, clear irq
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end
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end
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end
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end
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assign IRQ = |(UART_STATE^UART_STATEFF);
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assign IRQ = |(UART_STATE^UART_STATEFF);
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`ifdef __UARTQUEUE__
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assign DATAO = { UART_TIMER, UART_RFIFO[UART_RACK[7:0]], UART_STATE };
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`else
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assign DATAO = { UART_TIMER, UART_RFIFO, UART_STATE };
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assign DATAO = { UART_TIMER, UART_RFIFO, UART_STATE };
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`endif
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// xmit path: 6(IDLE), 7(START), 8, 9, 10, 11, 12, 13, 14, 15, 0(STOP), 1(ACK)
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// xmit path: 6(IDLE), 7(START), 8, 9, 10, 11, 12, 13, 14, 15, 0(STOP), 1(ACK)
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always@(posedge CLK)
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always@(posedge CLK)
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begin
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begin
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UART_XBAUD <= UART_XSTATE==`UART_STATE_IDLE ? UART_TIMER : // xbaud=timer
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UART_XBAUD <= UART_XSTATE==`UART_STATE_IDLE ? UART_TIMER : // xbaud=timer
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UART_XBAUD ? UART_XBAUD-1 : UART_TIMER; // while() { while(xbaud--); xbaud=timer }
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UART_XBAUD ? UART_XBAUD-1 : UART_TIMER; // while() { while(xbaud--); xbaud=timer }
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UART_XSTATE <= RES||UART_XSTATE==`UART_STATE_ACK ? `UART_STATE_IDLE :
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UART_XSTATE <= RES||UART_XSTATE==`UART_STATE_ACK ? `UART_STATE_IDLE :
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UART_XSTATE==`UART_STATE_IDLE ? UART_XSTATE+(UART_XREQ^UART_XACK) :
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UART_XSTATE==`UART_STATE_IDLE ? UART_XSTATE+(UART_XREQ!=UART_XACK) :
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UART_XSTATE+(UART_XBAUD==0);
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UART_XSTATE+(UART_XBAUD==0);
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`ifdef __UARTQUEUE__
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UART_XACK <= RES ? UART_XREQ : UART_XSTATE==`UART_STATE_ACK && UART_XACK!=UART_XREQ ? UART_XACK+1 : UART_XACK;
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`else
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UART_XACK <= RES||UART_XSTATE==`UART_STATE_ACK ? UART_XREQ : UART_XACK;
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UART_XACK <= RES||UART_XSTATE==`UART_STATE_ACK ? UART_XREQ : UART_XACK;
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`endif
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end
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end
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`ifdef __UARTQUEUE__
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assign UART_XTMP = UART_XFIFO[UART_XACK[7:0]];
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assign TXD = UART_XSTATE[3] ? UART_XTMP[UART_XSTATE[2:0]] : UART_XSTATE==`UART_STATE_START ? 0 : 1;
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`else
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assign TXD = UART_XSTATE[3] ? UART_XFIFO[UART_XSTATE[2:0]] : UART_XSTATE==`UART_STATE_START ? 0 : 1;
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assign TXD = UART_XSTATE[3] ? UART_XFIFO[UART_XSTATE[2:0]] : UART_XSTATE==`UART_STATE_START ? 0 : 1;
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`endif
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// recv path: 6(IDLE), 7(START), 8, 9, 10, 11, 12, 13, 14, 15, 0(STOP), 1(ACK)
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// recv path: 6(IDLE), 7(START), 8, 9, 10, 11, 12, 13, 14, 15, 0(STOP), 1(ACK)
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always@(posedge CLK)
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always@(posedge CLK)
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begin
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begin
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| Line 200... |
Line 251... |
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UART_RSTATE <= RES||UART_RSTATE==`UART_STATE_ACK ? `UART_STATE_IDLE :
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UART_RSTATE <= RES||UART_RSTATE==`UART_STATE_ACK ? `UART_STATE_IDLE :
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UART_RSTATE==`UART_STATE_IDLE ? UART_RSTATE+(UART_RXDFF[2:1]==2'b10) : // start bit detection
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UART_RSTATE==`UART_STATE_IDLE ? UART_RSTATE+(UART_RXDFF[2:1]==2'b10) : // start bit detection
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UART_RSTATE+(UART_RBAUD==0);
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UART_RSTATE+(UART_RBAUD==0);
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`ifdef __UARTQUEUE__
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if(UART_RSTATE==`UART_STATE_ACK&&(UART_RREQ!=(UART_RACK^9'h100)))
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begin
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UART_RREQ <= UART_RREQ+1;
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UART_RFIFO[UART_RREQ[7:0]] <= UART_RTMP;
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end
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`else
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UART_RREQ <= UART_RSTATE==`UART_STATE_ACK ? !UART_RACK : UART_RREQ;
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UART_RREQ <= UART_RSTATE==`UART_STATE_ACK ? !UART_RACK : UART_RREQ;
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`endif
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if(UART_RSTATE[3])
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if(UART_RSTATE[3])
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begin
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begin
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`ifdef __UARTQUEUE__
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UART_RTMP[UART_RSTATE[2:0]] <= UART_RXDFF[2];
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`else
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UART_RFIFO[UART_RSTATE[2:0]] <= UART_RXDFF[2];
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UART_RFIFO[UART_RSTATE[2:0]] <= UART_RXDFF[2];
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`endif
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end
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end
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end
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end
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//debug
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//debug
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