OpenCores
URL https://opencores.org/ocsvn/darkriscv/darkriscv/trunk

Subversion Repositories darkriscv

[/] [darkriscv/] [trunk/] [src/] [io.s] - Diff between revs 4 and 6

Show entire file | Details | Blame | View Log

Rev 4 Rev 6
Line 30... Line 30...
        beq     a0,a4,.L1
        beq     a0,a4,.L1
        .LA8: auipc     a5,%pcrel_hi(.LC8)
        .LA8: auipc     a5,%pcrel_hi(.LC8)
        li      a4,6
        li      a4,6
        addi    a5,a5,%pcrel_lo(.LA8)
        addi    a5,a5,%pcrel_lo(.LA8)
        beq     a0,a4,.L1
        beq     a0,a4,.L1
        .LA1: auipc     a5,%pcrel_hi(.LC1)
        .LA9: auipc     a5,%pcrel_hi(.LC9)
        li      a4,7
        li      a4,7
        addi    a5,a5,%pcrel_lo(.LA1)
        addi    a5,a5,%pcrel_lo(.LA9)
        beq     a0,a4,.L1
        beq     a0,a4,.L1
        .LA9: auipc     a5,%pcrel_hi(.LC9)
        .LA1: auipc     a5,%pcrel_hi(.LC1)
        li      a4,8
        li      a4,8
        addi    a5,a5,%pcrel_lo(.LA9)
        addi    a5,a5,%pcrel_lo(.LA1)
        beq     a0,a4,.L1
        beq     a0,a4,.L1
        .LA0: auipc     a5,%pcrel_hi(.LC0)
        .LA10: auipc    a5,%pcrel_hi(.LC10)
        li      a4,9
        li      a4,9
 
        addi    a5,a5,%pcrel_lo(.LA10)
 
        beq     a0,a4,.L1
 
        .LA0: auipc     a5,%pcrel_hi(.LC0)
 
        li      a4,10
        addi    a5,a5,%pcrel_lo(.LA0)
        addi    a5,a5,%pcrel_lo(.LA0)
        beq     a0,a4,.L1
        beq     a0,a4,.L1
        .LA10: auipc    a5,%pcrel_hi(.LC10)
        .LA11: auipc    a5,%pcrel_hi(.LC11)
        addi    a5,a5,%pcrel_lo(.LA10)
        addi    a5,a5,%pcrel_lo(.LA11)
.L1:
.L1:
        mv      a0,a5
        mv      a0,a5
        ret
        ret
        .size   board_name, .-board_name
        .size   board_name, .-board_name
        .globl  utimers
        .globl  utimers
        .globl  threads
        .globl  threads
        .comm   io,16,4
        .comm   io,16,4
        .section        .rodata.str1.4,"aMS",@progbits,1
        .section        .rodata.str1.4,"aMS",@progbits,1
        .align  2
        .align  2
.LC0:
.LC0:
        .string "qmtech artix7 a35"
        .string "aliexpress hpc/40gbe ku040"
        .zero   2
 
.LC1:
 
        .string "digilent spartan3 s200"
 
        .zero   1
        .zero   1
 
.LC1:
 
        .string "aliexpress hpc/40gbe k420"
 
        .zero   2
.LC2:
.LC2:
        .string "simulation only"
        .string "simulation only"
.LC3:
.LC3:
        .string "avnet microboard lx9"
        .string "avnet microboard lx9"
        .zero   3
        .zero   3
Line 79... Line 83...
        .zero   3
        .zero   3
.LC8:
.LC8:
        .string "piswords rs485 lx9"
        .string "piswords rs485 lx9"
        .zero   1
        .zero   1
.LC9:
.LC9:
        .string "aliexpress hpc/40gbe k420"
        .string "digilent spartan3 s200"
        .zero   2
        .zero   1
.LC10:
.LC10:
 
        .string "qmtech artix7 a35"
 
        .zero   2
 
.LC11:
        .string "unknown"
        .string "unknown"
        .section        .sbss,"aw",@nobits
        .section        .sbss,"aw",@nobits
        .align  2
        .align  2
        .type   utimers, @object
        .type   utimers, @object
        .size   utimers, 4
        .size   utimers, 4

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.