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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2004/01/16 14:53:33 mohor
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// *** empty log message ***
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//
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "dbg_cpu_defines.v"
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`include "dbg_cpu_defines.v"
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module dbg_cpu_registers (
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module dbg_cpu_registers (
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data_in,
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data_i,
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data_out,
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data_o,
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address,
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addr_i,
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rw,
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we_i,
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access,
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en_i,
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clk,
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clk_i,
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bp,
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bp_i,
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reset,
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rst_i,
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cpu_stall,
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cpu_clk_i,
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cpu_stall_all,
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cpu_stall_o,
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cpu_sel,
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cpu_stall_all_o,
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cpu_reset
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cpu_sel_o,
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cpu_rst_o
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);
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);
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input [7:0] data_in;
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input [7:0] data_i;
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input [1:0] address;
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input [1:0] addr_i;
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input rw;
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input access;
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input clk;
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input bp;
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input reset;
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output [7:0] data_out;
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reg [7:0] data_out;
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output cpu_stall;
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output cpu_stall_all;
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output [`CPU_NUM -1:0] cpu_sel;
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output cpu_reset;
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input we_i;
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input en_i;
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input clk_i;
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input bp_i;
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input rst_i;
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input cpu_clk_i;
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output [7:0] data_o;
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reg [7:0] data_o;
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output cpu_stall_o;
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output cpu_stall_all_o;
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output [`CPU_NUM -1:0] cpu_sel_o;
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output cpu_rst_o;
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wire cpu_stall;
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wire cpu_stall_all;
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wire cpu_reset;
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wire [2:1] cpu_op_out;
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wire [2:1] cpu_op_out;
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wire [`CPU_NUM -1:0] cpu_sel_out;
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wire [`CPU_NUM -1:0] cpu_sel_out;
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wire cpuop_wr;
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wire cpuop_wr;
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wire cpusel_wr;
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wire cpusel_wr;
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reg cpusel_wr_sync;
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reg cpusel_wr_cpu;
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reg cpu_stall_bp;
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reg cpu_stall_bp;
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reg cpu_stall_sync;
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reg cpu_stall_o;
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reg cpu_stall_all_sync;
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reg cpu_stall_all_o;
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reg cpu_reset_sync;
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reg cpu_rst_o;
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assign cpuop_wr = en_i & we_i & (addr_i == `CPU_OP_ADR);
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assign cpusel_wr = en_i & we_i & (addr_i == `CPU_SEL_ADR);
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assign cpuop_wr = access & rw & (address == `CPUOP_ADR);
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assign cpusel_wr = access & rw & (address == `CPUSEL_ADR);
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// Synchronising we for cpu_sel register that works in cpu_clk clock domain
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always @ (posedge cpu_clk_i)
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begin
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cpusel_wr_sync <= #1 cpusel_wr;
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cpusel_wr_cpu <= #1 cpusel_wr_sync;
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end
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always @(posedge clk or posedge reset)
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always @(posedge clk_i or posedge rst_i)
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begin
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begin
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if(reset)
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if(rst_i)
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cpu_stall_bp <= 1'b0;
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cpu_stall_bp <= 1'b0;
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else if(bp) // Breakpoint sets bit
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else if(bp_i) // Breakpoint sets bit
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cpu_stall_bp <= 1'b1;
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cpu_stall_bp <= 1'b1;
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else if(cpuop_wr) // Register access can set or clear bit
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else if(cpuop_wr) // Register access can set or clear bit
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cpu_stall_bp <= data_in[0];
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cpu_stall_bp <= data_i[0];
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end
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end
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dbg_register #(2, 0) CPUOP (.data_in(data_in[2:1]), .data_out(cpu_op_out[2:1]), .write(cpuop_wr), .clk(clk), .reset(reset));
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dbg_register #(2, 0) CPUOP (.data_in(data_i[2:1]), .data_out(cpu_op_out[2:1]), .write(cpuop_wr), .clk(clk_i), .reset(rst_i));
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dbg_register #(`CPU_NUM, 0) CPUSEL (.data_in(data_in[`CPU_NUM-1:0]), .data_out(cpu_sel_out), .write(cpusel_wr), .clk(clk), .reset(reset));
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dbg_register #(`CPU_NUM, 0) CPUSEL (.data_in(data_i[`CPU_NUM-1:0]), .data_out(cpu_sel_out), .write(cpusel_wr_cpu), .clk(cpu_clk_i), .reset(rst_i)); // cpu_cli_i
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always @ (posedge clk)
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always @ (posedge clk_i)
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begin
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begin
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case (address) // Synthesis parallel_case
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case (addr_i) // Synthesis parallel_case
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`CPUOP_ADR : data_out<= #1 {5'h0, cpu_op_out[2:1], cpu_stall};
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`CPU_OP_ADR : data_o <= #1 {5'h0, cpu_op_out[2:1], cpu_stall};
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`CPUSEL_ADR : data_out<= #1 {{(8-`CPU_NUM){1'b0}}, cpu_sel_out};
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`CPU_SEL_ADR : data_o <= #1 {{(8-`CPU_NUM){1'b0}}, cpu_sel_out};
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default : data_out<= #1 8'h0;
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default : data_o <= #1 8'h0;
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endcase
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endcase
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end
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end
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assign cpu_stall = bp | cpu_stall_bp; // bp asynchronously sets the cpu_stall, then cpu_stall_bp (from register) holds it active
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assign cpu_stall = bp_i | cpu_stall_bp; // bp asynchronously sets the cpu_stall, then cpu_stall_bp (from register) holds it active
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assign cpu_stall_all = cpu_op_out[2]; // this signal is used to stall all the cpus except the one that is selected in cpusel register
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assign cpu_stall_all = cpu_op_out[2]; // this signal is used to stall all the cpus except the one that is selected in cpusel register
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assign cpu_sel = cpu_sel_out;
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assign cpu_sel_o = cpu_sel_out;
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assign cpu_reset = cpu_op_out[1];
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assign cpu_reset = cpu_op_out[1];
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// Synchronizing signals from registers
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always @ (posedge cpu_clk_i)
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begin
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cpu_stall_sync <= #1 cpu_stall;
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cpu_stall_o <= #1 cpu_stall_sync;
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cpu_stall_all_sync <= #1 cpu_stall_all;
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cpu_stall_all_o <= #1 cpu_stall_all_sync;
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cpu_reset_sync <= #1 cpu_reset;
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cpu_rst_o <= #1 cpu_reset_sync;
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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