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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// dbg_cpu_registers.v ////
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//// dbg_cpu_registers.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// This file is part of the SoC Debug Interface. ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2004/03/22 16:35:46 igorm
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// Temp version before changing dbg interface.
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//
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// Revision 1.4 2004/01/25 14:04:18 mohor
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// Revision 1.4 2004/01/25 14:04:18 mohor
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// All flipflops are reset.
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// All flipflops are reset.
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//
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//
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// Revision 1.3 2004/01/22 10:16:08 mohor
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// Revision 1.3 2004/01/22 10:16:08 mohor
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// cpu_stall_o activated as soon as bp occurs.
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// cpu_stall_o activated as soon as bp occurs.
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// synopsys translate_on
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// synopsys translate_on
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`include "dbg_cpu_defines.v"
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`include "dbg_cpu_defines.v"
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module dbg_cpu_registers (
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module dbg_cpu_registers (
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data_i,
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data_i,
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data_o,
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addr_i,
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we_i,
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we_i,
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en_i,
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tck_i,
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clk_i,
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bp_i,
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bp_i,
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rst_i,
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rst_i,
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cpu_clk_i,
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cpu_clk_i,
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ctrl_reg_o,
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cpu_stall_o,
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cpu_stall_o,
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cpu_stall_all_o,
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cpu_sel_o,
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cpu_rst_o
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cpu_rst_o
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);
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);
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input [7:0] data_i;
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input [`DBG_CPU_CTRL_LEN -1:0] data_i;
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input [1:0] addr_i;
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input we_i;
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input we_i;
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input en_i;
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input tck_i;
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input clk_i;
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input bp_i;
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input bp_i;
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input rst_i;
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input rst_i;
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input cpu_clk_i;
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input cpu_clk_i;
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output [7:0] data_o;
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output [`DBG_CPU_CTRL_LEN -1:0]ctrl_reg_o;
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reg [7:0] data_o;
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output cpu_stall_o;
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output cpu_stall_o;
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output cpu_stall_all_o;
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output [`CPU_NUM -1:0] cpu_sel_o;
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output cpu_rst_o;
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output cpu_rst_o;
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wire cpu_stall_all;
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reg cpu_reset;
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wire cpu_reset;
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wire [2:1] cpu_op_out;
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wire [2:1] cpu_op_out;
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wire [`CPU_NUM -1:0] cpu_sel_out;
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wire cpuop_wr;
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reg stall_bp, stall_bp_csff, stall_bp_tck;
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wire cpusel_wr;
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reg stall_reg, stall_reg_csff, stall_reg_cpu;
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reg cpu_reset_csff;
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reg cpusel_wr_sync, cpusel_wr_cpu;
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reg stall_bp, stall_bp_sync, stall_bp_tck;
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reg stall_reg, stall_reg_sync, stall_reg_cpu;
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reg cpu_stall_all_sync;
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reg cpu_stall_all_o;
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reg cpu_reset_sync;
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reg cpu_rst_o;
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reg cpu_rst_o;
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assign cpuop_wr = en_i & we_i & (addr_i == `CPU_OP_ADR);
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assign cpusel_wr = en_i & we_i & (addr_i == `CPU_SEL_ADR);
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// Synchronising we for cpu_sel register that works in cpu_clk clock domain
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always @ (posedge cpu_clk_i or posedge rst_i)
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begin
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if (rst_i)
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begin
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cpusel_wr_sync <= #1 1'b0;
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cpusel_wr_cpu <= #1 1'b0;
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end
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else
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begin
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cpusel_wr_sync <= #1 cpusel_wr;
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cpusel_wr_cpu <= #1 cpusel_wr_sync;
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end
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end
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// Breakpoint is latched and synchronized. Stall is set and latched.
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// Breakpoint is latched and synchronized. Stall is set and latched.
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always @ (posedge cpu_clk_i or posedge rst_i)
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always @ (posedge cpu_clk_i or posedge rst_i)
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begin
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begin
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if(rst_i)
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if(rst_i)
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stall_bp <= #1 1'b0;
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stall_bp <= #1 1'b0;
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stall_bp <= #1 1'b0;
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stall_bp <= #1 1'b0;
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end
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end
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// Synchronizing
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// Synchronizing
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always @ (posedge clk_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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begin
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begin
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stall_bp_sync <= #1 1'b0;
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stall_bp_csff <= #1 1'b0;
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stall_bp_tck <= #1 1'b0;
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stall_bp_tck <= #1 1'b0;
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end
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end
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else
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else
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begin
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begin
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stall_bp_sync <= #1 stall_bp;
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stall_bp_csff <= #1 stall_bp;
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stall_bp_tck <= #1 stall_bp_sync;
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stall_bp_tck <= #1 stall_bp_csff;
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end
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end
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end
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end
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always @ (posedge clk_i or posedge rst_i)
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begin
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if (rst_i)
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stall_reg <= #1 1'b0;
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else if (stall_bp_tck)
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stall_reg <= #1 1'b1;
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else if (cpuop_wr)
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stall_reg <= #1 data_i[0];
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end
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always @ (posedge cpu_clk_i or posedge rst_i)
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always @ (posedge cpu_clk_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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begin
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begin
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stall_reg_sync <= #1 1'b0;
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stall_reg_csff <= #1 1'b0;
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stall_reg_cpu <= #1 1'b0;
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stall_reg_cpu <= #1 1'b0;
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end
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end
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else
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else
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begin
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begin
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stall_reg_sync <= #1 stall_reg;
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stall_reg_csff <= #1 stall_reg;
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stall_reg_cpu <= #1 stall_reg_sync;
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stall_reg_cpu <= #1 stall_reg_csff;
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end
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end
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end
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end
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assign cpu_stall_o = bp_i | stall_bp | stall_reg_cpu;
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assign cpu_stall_o = bp_i | stall_bp | stall_reg_cpu;
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// Writing data to the control registers (stall)
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dbg_register #(2, 0) CPUOP (.data_in(data_i[2:1]), .data_out(cpu_op_out[2:1]), .write(cpuop_wr), .clk(clk_i), .reset(rst_i));
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always @ (posedge tck_i or posedge rst_i)
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dbg_register #(`CPU_NUM, `CPU_NUM'h1) CPUSEL (.data_in(data_i[`CPU_NUM-1:0]), .data_out(cpu_sel_out), .write(cpusel_wr_cpu), .clk(cpu_clk_i), .reset(rst_i)); // cpu_cli_i
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always @ (posedge clk_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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data_o <= #1 8'h0;
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stall_reg <= #1 1'b0;
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else
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else if (stall_bp_tck)
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begin
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stall_reg <= #1 1'b1;
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case (addr_i) // Synthesis parallel_case
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else if (we_i)
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`CPU_OP_ADR : data_o <= #1 {5'h0, cpu_op_out[2:1], stall_reg};
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stall_reg <= #1 data_i[0];
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`CPU_SEL_ADR : data_o <= #1 {{(8-`CPU_NUM){1'b0}}, cpu_sel_out};
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default : data_o <= #1 8'h0;
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endcase
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end
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end
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end
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assign cpu_stall_all = cpu_op_out[2]; // this signal is used to stall all the cpus except the one that is selected in cpusel register
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// Writing data to the control registers (reset)
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assign cpu_sel_o = cpu_sel_out;
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always @ (posedge tck_i or posedge rst_i)
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assign cpu_reset = cpu_op_out[1];
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begin
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if (rst_i)
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cpu_reset <= #1 1'b0;
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else if(we_i)
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cpu_reset <= #1 data_i[1];
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end
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// Synchronizing signals from registers
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// Synchronizing signals from registers
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always @ (posedge cpu_clk_i or posedge rst_i)
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always @ (posedge cpu_clk_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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begin
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begin
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cpu_stall_all_sync <= #1 1'b0;
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cpu_reset_csff <= #1 1'b0;
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cpu_stall_all_o <= #1 1'b0;
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cpu_reset_sync <= #1 1'b0;
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cpu_rst_o <= #1 1'b0;
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cpu_rst_o <= #1 1'b0;
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end
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end
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else
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else
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begin
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begin
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cpu_stall_all_sync <= #1 cpu_stall_all;
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cpu_reset_csff <= #1 cpu_reset;
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cpu_stall_all_o <= #1 cpu_stall_all_sync;
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cpu_rst_o <= #1 cpu_reset_csff;
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cpu_reset_sync <= #1 cpu_reset;
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cpu_rst_o <= #1 cpu_reset_sync;
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end
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end
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end
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end
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// Value for read back
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assign ctrl_reg_o = {cpu_reset, stall_reg};
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endmodule
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endmodule
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