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[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] [verilog/] [dbg_wb.v] - Diff between revs 139 and 141

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Rev 139 Rev 141
Line 41... Line 41...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.20  2004/03/28 20:27:02  igorm
 
// New release of the debug interface (3rd. release).
 
//
// Revision 1.19  2004/03/22 16:35:46  igorm
// Revision 1.19  2004/03/22 16:35:46  igorm
// Temp version before changing dbg interface.
// Temp version before changing dbg interface.
//
//
// Revision 1.18  2004/01/25 14:04:18  mohor
// Revision 1.18  2004/01/25 14:04:18  mohor
// All flipflops are reset.
// All flipflops are reset.
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reg     [`DBG_WB_CRC_CNT_WIDTH -1:0] crc_cnt;
reg     [`DBG_WB_CRC_CNT_WIDTH -1:0] crc_cnt;
wire          crc_cnt_end;
wire          crc_cnt_end;
reg           crc_cnt_end_q;
reg           crc_cnt_end_q;
reg           data_cnt_en;
reg           data_cnt_en;
reg    [`DBG_WB_DATA_CNT_WIDTH:0] data_cnt;
reg    [`DBG_WB_DATA_CNT_WIDTH:0] data_cnt;
reg    [`DBG_WB_DATA_CNT_WIDTH:0] data_cnt_limit;
reg    [`DBG_WB_DATA_CNT_LIM_WIDTH:0] data_cnt_limit;
wire          data_cnt_end;
wire          data_cnt_end;
reg           data_cnt_end_q;
reg           data_cnt_end_q;
 
 
reg           crc_match_reg;
reg           crc_match_reg;
 
 
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// Upper limit. Data counter counts until this value is reached.
// Upper limit. Data counter counts until this value is reached.
always @ (posedge tck_i or posedge rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
begin
  if (rst_i)
  if (rst_i)
    data_cnt_limit <= #1 {`DBG_WB_DATA_CNT_WIDTH{1'b0}};
    data_cnt_limit <= #1 {`DBG_WB_DATA_CNT_LIM_WIDTH{1'b0}};
  else if (update_dr_i)
  else if (update_dr_i)
    data_cnt_limit <= #1 {len + 1'b1, 3'b000};
    data_cnt_limit <= #1 len + 1'b1;
end
end
 
 
 
 
always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
begin
begin
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assign cmd_cnt_end      = cmd_cnt      == `DBG_WB_CMD_LEN;
assign cmd_cnt_end      = cmd_cnt      == `DBG_WB_CMD_LEN;
assign addr_len_cnt_end = addr_len_cnt == `DBG_WB_DR_LEN;
assign addr_len_cnt_end = addr_len_cnt == `DBG_WB_DR_LEN;
assign crc_cnt_end      = crc_cnt      == `DBG_WB_CRC_CNT_WIDTH'd32;
assign crc_cnt_end      = crc_cnt      == `DBG_WB_CRC_CNT_WIDTH'd32;
assign crc_cnt_31       = crc_cnt      == `DBG_WB_CRC_CNT_WIDTH'd31;
assign crc_cnt_31       = crc_cnt      == `DBG_WB_CRC_CNT_WIDTH'd31;
assign data_cnt_end     = (data_cnt    == data_cnt_limit);
assign data_cnt_end     = (data_cnt    == {data_cnt_limit, 3'b000});
 
 
always @ (posedge tck_i or posedge rst_i)
always @ (posedge tck_i or posedge rst_i)
begin
begin
  if (rst_i)
  if (rst_i)
    begin
    begin
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  else if (status_cnt_en)
  else if (status_cnt_en)
    status_cnt <= #1 status_cnt + 1'b1;
    status_cnt <= #1 status_cnt + 1'b1;
end
end
 
 
 
 
always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or acc_type_write or data_cnt_end or addr_len_cnt_end)
always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or acc_type_write or acc_type_read or data_cnt_end or addr_len_cnt_end)
begin
begin
  if (enable && (!status_cnt_end))
  if (enable && (!status_cnt_end))
    begin
    begin
      if (crc_cnt_end && curr_cmd_wr_comm)
      if (crc_cnt_end && curr_cmd_wr_comm)
        status_cnt_en = 1'b1;
        status_cnt_en = 1'b1;
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assign fifo_empty = fifo_cnt == 3'h0;
assign fifo_empty = fifo_cnt == 3'h0;
 
 
reg [799:0] tdo_text;
reg [799:0] tdo_text;
 
 
// TDO multiplexer
// TDO multiplexer
always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status or addr_len_cnt_end or addr_len_cnt_end_q)
always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or
 
          curr_cmd_rd_comm or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i
 
          or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status
 
          or addr_len_cnt_end or addr_len_cnt_end_q)
begin
begin
  if (pause_dr_i)
  if (pause_dr_i)
    begin
    begin
    tdo_o = busy_tck;
    tdo_o = busy_tck;
    tdo_text = "busy_tck";
    tdo_text = "busy_tck";

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