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Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2004/03/31 14:34:09 igorm
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// data_cnt_lim length changed to reduce number of warnings.
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//
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// Revision 1.8 2004/03/28 20:27:01 igorm
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// Revision 1.8 2004/03/28 20:27:01 igorm
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// New release of the debug interface (3rd. release).
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// New release of the debug interface (3rd. release).
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//
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//
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// Revision 1.7 2004/01/25 14:04:18 mohor
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// Revision 1.7 2004/01/25 14:04:18 mohor
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// All flipflops are reset.
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// All flipflops are reset.
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| Line 235... |
Line 238... |
assign acc_type_read = (acc_type == `DBG_CPU_READ);
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assign acc_type_read = (acc_type == `DBG_CPU_READ);
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assign acc_type_write = (acc_type == `DBG_CPU_WRITE);
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assign acc_type_write = (acc_type == `DBG_CPU_WRITE);
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reg [799:0] dr_text;
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// Shift register for shifting in and out the data
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// Shift register for shifting in and out the data
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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begin
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begin
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latch_data <= #1 1'b0;
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latch_data <= #1 1'b0;
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dr <= #1 {`DBG_CPU_DR_LEN{1'b0}};
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dr <= #1 {`DBG_CPU_DR_LEN{1'b0}};
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dr_text = "reset";
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end
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end
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else if (curr_cmd_rd_comm && crc_cnt_31) // Latching data (from internal regs)
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else if (curr_cmd_rd_comm && crc_cnt_31) // Latching data (from internal regs)
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begin
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begin
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dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1:0] <= #1 {acc_type, adr, len};
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dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1:0] <= #1 {acc_type, adr, len};
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dr_text = "latch reg data";
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end
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end
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else if (curr_cmd_rd_ctrl && crc_cnt_31) // Latching data (from control regs)
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else if (curr_cmd_rd_ctrl && crc_cnt_31) // Latching data (from control regs)
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begin
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begin
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dr[`DBG_CPU_DR_LEN -1:`DBG_CPU_DR_LEN -`DBG_CPU_CTRL_LEN] <= #1 ctrl_reg;
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dr[`DBG_CPU_DR_LEN -1:`DBG_CPU_DR_LEN -`DBG_CPU_CTRL_LEN] <= #1 ctrl_reg;
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dr_text = "latch ctrl reg data";
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end
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end
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else if (acc_type_read && curr_cmd_go && crc_cnt_31) // Latchind first data (from WB)
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else if (acc_type_read && curr_cmd_go && crc_cnt_31) // Latchind first data (from WB)
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begin
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begin
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dr[31:0] <= #1 input_data[31:0];
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dr[31:0] <= #1 input_data[31:0];
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latch_data <= #1 1'b1;
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latch_data <= #1 1'b1;
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dr_text = "latch first data";
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end
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end
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else if (acc_type_read && curr_cmd_go && crc_cnt_end) // Latching data (from WB)
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else if (acc_type_read && curr_cmd_go && crc_cnt_end) // Latching data (from WB)
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begin
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begin
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case (acc_type) // synthesis parallel_case full_case
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case (acc_type) // synthesis parallel_case full_case
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`DBG_CPU_READ: begin
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`DBG_CPU_READ: begin
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if(long & (~long_q))
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if(long & (~long_q))
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begin
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begin
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dr[31:0] <= #1 input_data[31:0];
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dr[31:0] <= #1 input_data[31:0];
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latch_data <= #1 1'b1;
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latch_data <= #1 1'b1;
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dr_text = "latch_data word";
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end
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end
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else
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else
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begin
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begin
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dr[31:0] <= #1 {dr[30:0], 1'b0};
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dr[31:0] <= #1 {dr[30:0], 1'b0};
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latch_data <= #1 1'b0;
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latch_data <= #1 1'b0;
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dr_text = "shift word";
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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else if (enable && (!addr_len_cnt_end))
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else if (enable && (!addr_len_cnt_end))
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begin
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begin
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dr <= #1 {dr[`DBG_CPU_DR_LEN -2:0], tdi_i};
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dr <= #1 {dr[`DBG_CPU_DR_LEN -2:0], tdi_i};
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dr_text = "shift dr";
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end
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end
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end
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end
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Line 857... |
else if (!(cpu_end_tck && (!cpu_end_tck_q)) && latch_data && (fifo_full)) // decrementing
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else if (!(cpu_end_tck && (!cpu_end_tck_q)) && latch_data && (fifo_full)) // decrementing
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fifo_full <= #1 1'h0;
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fifo_full <= #1 1'h0;
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end
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end
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reg [799:0] tdo_text;
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// TDO multiplexer
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// TDO multiplexer
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always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status or addr_len_cnt_end or addr_len_cnt_end_q or curr_cmd_rd_comm or curr_cmd_rd_ctrl)
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always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status or addr_len_cnt_end or addr_len_cnt_end_q or curr_cmd_rd_comm or curr_cmd_rd_ctrl)
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begin
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begin
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if (pause_dr_i)
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if (pause_dr_i)
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begin
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begin
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tdo_o = busy_tck;
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tdo_o = busy_tck;
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tdo_text = "busy_tck";
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end
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end
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else if (crc_cnt_end && (!crc_cnt_end_q) && (curr_cmd_wr_comm || curr_cmd_wr_ctrl || curr_cmd_go && acc_type_write ))
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else if (crc_cnt_end && (!crc_cnt_end_q) && (curr_cmd_wr_comm || curr_cmd_wr_ctrl || curr_cmd_go && acc_type_write ))
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begin
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begin
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tdo_o = ~crc_match_i;
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tdo_o = ~crc_match_i;
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tdo_text = "crc_match_i";
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end
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end
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else if (curr_cmd_go && acc_type_read && crc_cnt_end && (!data_cnt_end))
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else if (curr_cmd_go && acc_type_read && crc_cnt_end && (!data_cnt_end))
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begin
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begin
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tdo_o = dr[31];
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tdo_o = dr[31];
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tdo_text = "dr[31]";
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end
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end
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else if (curr_cmd_go && acc_type_read && data_cnt_end && (!data_cnt_end_q))
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else if (curr_cmd_go && acc_type_read && data_cnt_end && (!data_cnt_end_q))
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begin
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begin
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tdo_o = ~crc_match_reg;
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tdo_o = ~crc_match_reg;
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tdo_text = "crc_match_reg";
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end
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end
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else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && addr_len_cnt_end && (!addr_len_cnt_end_q))
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else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && addr_len_cnt_end && (!addr_len_cnt_end_q))
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begin
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begin
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tdo_o = ~crc_match_reg;
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tdo_o = ~crc_match_reg;
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tdo_text = "crc_match_reg_rd_comm";
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end
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end
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else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && crc_cnt_end && (!addr_len_cnt_end))
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else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && crc_cnt_end && (!addr_len_cnt_end))
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begin
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begin
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tdo_o = dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1];
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tdo_o = dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1];
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tdo_text = "rd_comm | rd_ctrl data";
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end
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end
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else if (status_cnt_en)
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else if (status_cnt_en)
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begin
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begin
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tdo_o = status[3];
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tdo_o = status[3];
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tdo_text = "status";
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end
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end
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else
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else
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begin
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begin
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tdo_o = 1'b0;
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tdo_o = 1'b0;
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tdo_text = "zero";
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end
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end
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end
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end
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reg [799:0] status_text;
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// Status register
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// Status register
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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begin
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begin
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status <= #1 {`DBG_CPU_STATUS_LEN{1'b0}};
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status <= #1 {`DBG_CPU_STATUS_LEN{1'b0}};
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status_text = "reset";
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end
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end
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else if(crc_cnt_end && (!crc_cnt_end_q) && (!(curr_cmd_go && acc_type_read)))
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else if(crc_cnt_end && (!crc_cnt_end_q) && (!(curr_cmd_go && acc_type_read)))
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begin
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begin
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status <= #1 {1'b0, 1'b0, cpu_overrun_tck, crc_match_i};
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status <= #1 {1'b0, 1'b0, cpu_overrun_tck, crc_match_i};
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status_text = "latch ni read";
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end
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end
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else if (data_cnt_end && (!data_cnt_end_q) && curr_cmd_go && acc_type_read)
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else if (data_cnt_end && (!data_cnt_end_q) && curr_cmd_go && acc_type_read)
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begin
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begin
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status <= #1 {1'b0, 1'b0, underrun_tck, crc_match_reg};
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status <= #1 {1'b0, 1'b0, underrun_tck, crc_match_reg};
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status_text = "latch read";
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end
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end
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else if (addr_len_cnt_end && (!addr_len_cnt_end) && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
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else if (addr_len_cnt_end && (!addr_len_cnt_end) && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
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begin
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begin
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status <= #1 {1'b0, 1'b0, 1'b0, crc_match_reg};
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status <= #1 {1'b0, 1'b0, 1'b0, crc_match_reg};
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status_text = "rd_comm | rd_ctrl";
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end
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end
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else if (shift_dr_i && (!status_cnt_end))
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else if (shift_dr_i && (!status_cnt_end))
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begin
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begin
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status <= #1 {status[`DBG_CPU_STATUS_LEN -2:0], status[`DBG_CPU_STATUS_LEN -1]};
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status <= #1 {status[`DBG_CPU_STATUS_LEN -2:0], status[`DBG_CPU_STATUS_LEN -1]};
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status_text = "shifting";
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end
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end
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end
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end
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// Following status is shifted out (MSB first):
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// Following status is shifted out (MSB first):
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// 3. bit: 1 if crc is OK, else 0
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// 3. bit: 1 if crc is OK, else 0
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// 2. bit: 1'b0
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// 2. bit: 1'b0
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