| Line 1... |
Line 1... |
// igor !!! cmd_old_read poskusi dati ven
|
|
|
|
|
|
|
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// dbg_wb.v ////
|
//// dbg_wb.v ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
| Line 45... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.9 2004/01/10 07:50:24 mohor
|
|
// temp version.
|
|
//
|
// Revision 1.8 2004/01/09 12:48:44 mohor
|
// Revision 1.8 2004/01/09 12:48:44 mohor
|
// tmp version.
|
// tmp version.
|
//
|
//
|
// Revision 1.7 2004/01/08 17:53:36 mohor
|
// Revision 1.7 2004/01/08 17:53:36 mohor
|
// tmp version.
|
// tmp version.
|
| Line 210... |
Line 209... |
reg busy_tck;
|
reg busy_tck;
|
reg wb_end;
|
reg wb_end;
|
reg wb_end_rst;
|
reg wb_end_rst;
|
reg wb_end_rst_sync;
|
reg wb_end_rst_sync;
|
reg wb_end_sync;
|
reg wb_end_sync;
|
reg wb_end_tck;
|
reg wb_end_tck, wb_end_tck_q;
|
reg busy_sync;
|
reg busy_sync;
|
reg [799:0] TDO_WISHBONE;
|
reg [799:0] TDO_WISHBONE;
|
reg [399:0] latching_data;
|
reg [399:0] latching_data;
|
|
|
reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
|
reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
|
reg read_cycle;
|
reg read_cycle;
|
reg [2:0] read_type;
|
reg [2:0] read_type;
|
wire [31:0] input_data;
|
wire [31:0] input_data;
|
|
|
|
wire len_eq_0;
|
|
wire crc_cnt_31;
|
|
|
assign enable = wishbone_ce_i & shift_dr_i;
|
assign enable = wishbone_ce_i & shift_dr_i;
|
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
|
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
|
assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
|
assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
|
|
|
|
reg [1:0] ptr;
|
|
|
//always @ (posedge tck_i)
|
//always @ (posedge tck_i)
|
//begin
|
//begin
|
// if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
|
// if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
|
// dr <= #1 {dr[49:0], tdi_i};
|
// dr <= #1 {dr[49:0], tdi_i};
|
//end
|
//end
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
// if (cmd_old_read & cmd_go)
|
if (update_dr_i)
|
if (read_cycle & cmd_go)
|
ptr <= #1 2'h0;
|
|
else if (read_cycle & dr_go_latched & crc_cnt_31) // first latch
|
|
ptr <= #1 ptr + 1'b1;
|
|
else if (read_cycle & cmd_go & byte & (~byte_q))
|
|
ptr <= ptr + 1'd1;
|
|
end
|
|
|
|
|
|
|
|
always @ (posedge tck_i)
|
|
begin
|
|
if (read_cycle & dr_go_latched & crc_cnt_31)
|
|
begin
|
|
dr[31:0] <= #1 input_data[31:0];
|
|
latching_data = "First latch";
|
|
end
|
|
else if (read_cycle & crc_cnt_end)
|
begin
|
begin
|
// case (cmd_old) // synthesis parallel_case full_case
|
|
case (read_type) // synthesis parallel_case full_case
|
case (read_type) // synthesis parallel_case full_case
|
`WB_READ8 : begin
|
`WB_READ8 : begin
|
if(byte & (~byte_q))
|
if(byte & (~byte_q))
|
begin
|
begin
|
dr[31:24] <= #1 8'h08; // input_data[];
|
case (ptr) // synthesis parallel_case
|
|
2'b00 : dr[31:24] <= #1 input_data[31:24];
|
|
2'b01 : dr[31:24] <= #1 input_data[23:16];
|
|
2'b10 : dr[31:24] <= #1 input_data[15:8];
|
|
2'b11 : dr[31:24] <= #1 input_data[7:0];
|
|
endcase
|
latching_data = "8 bit latched";
|
latching_data = "8 bit latched";
|
end
|
end
|
else
|
else
|
begin
|
begin
|
dr[31:0] <= #1 {dr[30:0], 1'b0};
|
dr[31:24] <= #1 {dr[30:24], 1'b0};
|
latching_data = "8 bit shifted";
|
latching_data = "8 bit shifted";
|
end
|
end
|
end
|
end
|
`WB_READ16: begin
|
`WB_READ16: begin
|
if(half & (~half_q))
|
if(half & (~half_q))
|
begin
|
begin
|
dr[31:16] <= #1 16'h1616;
|
if (ptr[1])
|
|
dr[31:16] <= #1 input_data[31:16];
|
|
else
|
|
dr[31:16] <= #1 input_data[15:0];
|
latching_data = "16 bit latched";
|
latching_data = "16 bit latched";
|
end
|
end
|
else
|
else
|
begin
|
begin
|
dr[31:0] <= #1 {dr[30:0], 1'b0};
|
dr[31:16] <= #1 {dr[30:16], 1'b0};
|
latching_data = "16 bit shifted";
|
latching_data = "16 bit shifted";
|
end
|
end
|
end
|
end
|
`WB_READ32: begin
|
`WB_READ32: begin
|
if(long & (~long_q))
|
if(long & (~long_q))
|
begin
|
begin
|
dr[31:0] <= #1 32'h32323232;
|
dr[31:0] <= #1 input_data[31:0];
|
latching_data = "32 bit latched";
|
latching_data = "32 bit latched";
|
end
|
end
|
else
|
else
|
begin
|
begin
|
dr[31:0] <= #1 {dr[30:0], 1'b0};
|
dr[31:0] <= #1 {dr[30:0], 1'b0};
|
| Line 318... |
Line 344... |
begin
|
begin
|
if (trst_i)
|
if (trst_i)
|
data_cnt <= #1 'h0;
|
data_cnt <= #1 'h0;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
data_cnt <= #1 'h0;
|
data_cnt <= #1 'h0;
|
|
// else if (crc_cnt_31 & dr_go_latched & cmd_read)
|
|
// data_cnt <= #1 'h1;
|
else if (data_cnt_en)
|
else if (data_cnt_en)
|
data_cnt <= #1 data_cnt + 1'b1;
|
data_cnt <= #1 data_cnt + 1'b1;
|
end
|
end
|
|
|
|
|
|
|
assign byte = data_cnt[2:0] == 3'h0;
|
assign byte = data_cnt[2:0] == 3'd7;
|
assign half = data_cnt[3:0] == 4'h0;
|
assign half = data_cnt[3:0] == 4'd15;
|
assign long = data_cnt[4:0] == 5'h0;
|
assign long = data_cnt[4:0] == 5'd31;
|
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
// if (crc_cnt == 6'd31) // Reset to zero after crc to load first data byte. igor !!! This is probably not necessary
|
// if (crc_cnt == 6'd31) // Reset to zero after crc to load first data byte. igor !!! This is probably not necessary
|
| Line 395... |
Line 423... |
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (update_dr_i)
|
if (update_dr_i)
|
data_cnt_limit = 19'h0;
|
data_cnt_limit = 19'h0;
|
else if (((cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i) & cmd_write) | // current command is WB_GO and previous command is WB_WRITEx)
|
else if (((cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i) & cmd_write) | // current command is WB_GO and previous command is WB_WRITEx)
|
((crc_cnt == 6'd31) & dr_go_latched & cmd_read) // current command is WB_GO and previous command is WB_READx)
|
(crc_cnt_31 & dr_go_latched & cmd_read) // current command is WB_GO and previous command is WB_READx)
|
)
|
)
|
data_cnt_limit = {len, 3'b000};
|
data_cnt_limit = {len, 3'b000};
|
end
|
end
|
|
|
|
|
| Line 417... |
Line 445... |
end
|
end
|
|
|
assign cmd_cnt_end = cmd_cnt == 2'h3;
|
assign cmd_cnt_end = cmd_cnt == 2'h3;
|
assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
|
assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
|
assign crc_cnt_end = crc_cnt == 6'd32;
|
assign crc_cnt_end = crc_cnt == 6'd32;
|
|
assign crc_cnt_31 = crc_cnt == 6'd31;
|
assign data_cnt_end = (data_cnt == data_cnt_limit);
|
assign data_cnt_end = (data_cnt == data_cnt_limit);
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
crc_cnt_end_q <= #1 crc_cnt_end;
|
crc_cnt_end_q <= #1 crc_cnt_end;
|
| Line 499... |
Line 528... |
// 3. bit: 1 if overrun occured during write (data couldn't be written fast enough)
|
// 3. bit: 1 if overrun occured during write (data couldn't be written fast enough)
|
// 4. bit: 1 if WB error occured, else 0
|
// 4. bit: 1 if WB error occured, else 0
|
|
|
|
|
|
|
always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck or cmd_read or data_cnt_end or data_cnt_end_q or crc_match_reg or dr_read_latched)
|
always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or dr_go_latched or cmd_read or
|
|
crc_match_i or data_cnt_end or data_cnt_end_q or read_cycle or crc_match_reg or status or
|
|
dr or cmd_go)
|
begin
|
begin
|
if (pause_dr_i)
|
if (pause_dr_i)
|
begin
|
begin
|
tdo_o = busy_tck;
|
tdo_o = busy_tck;
|
TDO_WISHBONE = "busy_tck";
|
TDO_WISHBONE = "busy_tck";
|
| Line 511... |
Line 542... |
else if (crc_cnt_end & (~crc_cnt_end_q) & (~(dr_go_latched & cmd_read))) // cmd is updated not updated, yet
|
else if (crc_cnt_end & (~crc_cnt_end_q) & (~(dr_go_latched & cmd_read))) // cmd is updated not updated, yet
|
begin
|
begin
|
tdo_o = crc_match_i;
|
tdo_o = crc_match_i;
|
TDO_WISHBONE = "crc_match_i";
|
TDO_WISHBONE = "crc_match_i";
|
end
|
end
|
// else if (data_cnt_end & (~data_cnt_end_q) & dr_go_latched & cmd_old_read) // cmd is already updated
|
else if (read_cycle & crc_cnt_end & (~data_cnt_end))
|
|
begin
|
|
tdo_o = dr[31];
|
|
TDO_WISHBONE = "read data";
|
|
end
|
else if (data_cnt_end & (~data_cnt_end_q) & read_cycle) // cmd is already updated
|
else if (data_cnt_end & (~data_cnt_end_q) & read_cycle) // cmd is already updated
|
begin
|
begin
|
tdo_o = crc_match_reg;
|
tdo_o = crc_match_reg;
|
TDO_WISHBONE = "crc_match_reg";
|
TDO_WISHBONE = "crc_match_reg";
|
end
|
end
|
// else if (crc_cnt_end & (~read_cycle) | data_cnt_end & read_cycle) // cmd is already updated
|
|
else if (crc_cnt_end & data_cnt_end) // cmd is already updated
|
else if (crc_cnt_end & data_cnt_end) // cmd is already updated
|
begin
|
begin
|
tdo_o = status[0];
|
tdo_o = status[0];
|
TDO_WISHBONE = "status";
|
TDO_WISHBONE = "status";
|
end
|
end
|
| Line 588... |
Line 622... |
if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
begin
|
begin
|
if (dr_write_latched | dr_read_latched)
|
if (dr_write_latched | dr_read_latched)
|
begin
|
begin
|
adr <= #1 dr[47:16];
|
adr <= #1 dr[47:16];
|
len <= #1 dr[15:0];
|
|
set_addr <= #1 1'b1;
|
set_addr <= #1 1'b1;
|
end
|
end
|
end
|
end
|
else
|
else
|
set_addr <= #1 1'b0;
|
set_addr <= #1 1'b0;
|
end
|
end
|
|
|
|
|
|
always @ (posedge tck_i)
|
|
begin
|
|
if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (dr_write_latched | dr_read_latched))
|
|
len <= #1 dr[15:0];
|
|
else if (wb_end_tck & (~wb_end_tck_q))
|
|
begin
|
|
case (read_type) // synthesis parallel_case full_case
|
|
`WB_READ8 : len <= #1 len - 1'd1;
|
|
`WB_READ16: len <= #1 len - 2'd2;
|
|
`WB_READ32: len <= #1 len - 3'd4;
|
|
endcase
|
|
end
|
|
end
|
|
|
|
|
|
assign len_eq_0 = len == 16'h0;
|
|
|
|
|
|
|
// Start wishbone read cycle
|
// Start wishbone read cycle
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
// if (set_addr & dr_read_latched)
|
if (cmd_cnt_end & (~cmd_cnt_end_q) & cmd_read & dr_go) // First read after cmd is entered igor !!! Add something to block too many accesses.
|
if (cmd_cnt_end & (~cmd_cnt_end_q) & cmd_read & dr_go)
|
|
start_rd_tck <= #1 1'b1;
|
start_rd_tck <= #1 1'b1;
|
// else if (cmd_old_read & cmd_go & crc_cnt_end_q & (~data_cnt_end))
|
else if (read_cycle & dr_go_latched & crc_cnt_end & (~crc_cnt_end_q) & (~len_eq_0)) // Second read after first data is latched igor !!! Add something to block too many accesses.
|
else if (read_cycle)
|
start_rd_tck <= #1 1'b1;
|
|
else if (read_cycle & (~len_eq_0))
|
begin
|
begin
|
case (read_type) // synthesis parallel_case full_case
|
case (read_type) // synthesis parallel_case full_case
|
`WB_READ8 : begin
|
`WB_READ8 : begin
|
if(byte & (~byte_q))
|
if(byte & (~byte_q))
|
start_rd_tck <= #1 1'b1;
|
start_rd_tck <= #1 1'b1;
|
| Line 794... |
Line 847... |
begin
|
begin
|
if (trst_i)
|
if (trst_i)
|
begin
|
begin
|
wb_end_sync <= #1 1'b0;
|
wb_end_sync <= #1 1'b0;
|
wb_end_tck <= #1 1'b0;
|
wb_end_tck <= #1 1'b0;
|
|
wb_end_tck_q<= #1 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
wb_end_sync <= #1 wb_end;
|
wb_end_sync <= #1 wb_end;
|
wb_end_tck <= #1 wb_end_sync;
|
wb_end_tck <= #1 wb_end_sync;
|
|
wb_end_tck_q<= #1 wb_end_tck;
|
end
|
end
|
end
|
end
|
|
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
| Line 937... |
Line 992... |
begin
|
begin
|
case (wb_sel_o) // synthesis parallel_case full_case
|
case (wb_sel_o) // synthesis parallel_case full_case
|
4'b1000 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[31:24]; // byte
|
4'b1000 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[31:24]; // byte
|
4'b0100 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[23:16]; // byte
|
4'b0100 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[23:16]; // byte
|
4'b0010 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[15:08]; // byte
|
4'b0010 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[15:08]; // byte
|
4'b0001 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[07:01]; // byte
|
4'b0001 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[07:00]; // byte
|
|
|
4'b1100 : // half
|
4'b1100 : // half
|
begin
|
begin
|
mem[mem_ptr[1:0]] <= #1 wb_dat_i[31:24];
|
mem[mem_ptr[1:0]] <= #1 wb_dat_i[31:24];
|
mem[mem_ptr[1:0]+1'b1] <= #1 wb_dat_i[23:16];
|
mem[mem_ptr[1:0]+1'b1] <= #1 wb_dat_i[23:16];
|
end
|
end
|
4'b0011 : // half
|
4'b0011 : // half
|
begin
|
begin
|
mem[mem_ptr[1:0]] <= #1 wb_dat_i[15:08];
|
mem[mem_ptr[1:0]] <= #1 wb_dat_i[15:08];
|
mem[mem_ptr[1:0]+1'b1] <= #1 wb_dat_i[07:01];
|
mem[mem_ptr[1:0]+1'b1] <= #1 wb_dat_i[07:00];
|
end
|
end
|
4'b1111 : // long
|
4'b1111 : // long
|
begin
|
begin
|
mem[0] <= #1 wb_dat_i[31:24];
|
mem[0] <= #1 wb_dat_i[31:24];
|
mem[1] <= #1 wb_dat_i[23:16];
|
mem[1] <= #1 wb_dat_i[23:16];
|
mem[2] <= #1 wb_dat_i[15:08];
|
mem[2] <= #1 wb_dat_i[15:08];
|
mem[3] <= #1 wb_dat_i[07:01];
|
mem[3] <= #1 wb_dat_i[07:00];
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
| Line 966... |
Line 1021... |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
