| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.20 2004/01/09 12:49:23 mohor
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// tmp version.
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//
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// Revision 1.19 2004/01/08 17:53:12 mohor
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// Revision 1.19 2004/01/08 17:53:12 mohor
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// tmp version.
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// tmp version.
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//
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//
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// Revision 1.18 2004/01/07 11:59:48 mohor
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// Revision 1.18 2004/01/07 11:59:48 mohor
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// temp4 version.
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// temp4 version.
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| Line 360... |
Line 363... |
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#10000;
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#10000;
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debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 32'hc7b0424d, result, "status 2"); // {command, ready, addr, length, crc, result, text}
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debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 32'hc7b0424d, result, "status 2"); // {command, ready, addr, length, crc, result, text}
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#10000;
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#10000;
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wb_slave.cycle_response(`ACK_RESPONSE, 8'h4a, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
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wb_slave.cycle_response(`ACK_RESPONSE, 8'h0a, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
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debug_wishbone(`WB_READ32, 1'b1, 32'h12347778, 16'hc, 32'hd9ce3bbe, result, "read32 5"); // {command, ready, addr, length, crc, result, text}
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debug_wishbone(`WB_READ32, 1'b1, 32'h12347778, 16'hc, 32'hd9ce3bbe, result, "read32 5"); // {command, ready, addr, length, crc, result, text}
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#10000;
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#10000;
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debug_wishbone(`WB_WRITE32, 1'b0, 32'h12346668, 16'h8, 32'hc5a58ff5, result, "wr32 len8"); // {command, ready, addr, length, crc, result, text}
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debug_wishbone(`WB_WRITE32, 1'b0, 32'h12346668, 16'h8, 32'hc5a58ff5, result, "wr32 len8"); // {command, ready, addr, length, crc, result, text}
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| Line 681... |
Line 684... |
begin
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begin
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tdi_pad_i<=#1 crc[i];
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tdi_pad_i<=#1 crc[i];
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gen_clk(1);
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gen_clk(1);
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end
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end
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tdi_pad_i<=#1 'hz;
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if (wait_for_wb_ready)
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if (wait_for_wb_ready)
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begin
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begin
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gen_clk(`STATUS_LEN -1); // Generating 4 clocks to read out status. Going to pause_dr at the end
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gen_clk(`STATUS_LEN -1); // Generating 4 clocks to read out status. Going to pause_dr at the end
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tdi_pad_i<=#1 'hz;
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tms_pad_i<=#1 1;
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tms_pad_i<=#1 1;
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gen_clk(1); // to exit1_dr
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gen_clk(1); // to exit1_dr
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tms_pad_i<=#1 0;
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tms_pad_i<=#1 0;
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gen_clk(1); // to pause_dr
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gen_clk(1); // to pause_dr
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| Line 705... |
Line 708... |
else
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else
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gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
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gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
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for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
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for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
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begin
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begin
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tdi_pad_i<=#1 1'b0;
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gen_clk(1);
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gen_clk(1);
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end
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end
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tdi_pad_i<=#1 crc[i]; // last crc
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tms_pad_i<=#1 1;
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tms_pad_i<=#1 1;
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gen_clk(1); // to exit1_dr
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gen_clk(1); // to exit1_dr
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tdi_pad_i<=#1 'hz; // tri-state
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tms_pad_i<=#1 1;
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tms_pad_i<=#1 1;
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gen_clk(1); // to update_dr
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gen_clk(1); // to update_dr
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tms_pad_i<=#1 0;
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tms_pad_i<=#1 0;
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gen_clk(1); // to run_test_idle
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gen_clk(1); // to run_test_idle
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end
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end
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| Line 753... |
Line 753... |
begin
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begin
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tdi_pad_i<=#1 crc[i];
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tdi_pad_i<=#1 crc[i];
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gen_clk(1);
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gen_clk(1);
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end
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end
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tdi_pad_i<=#1 1'hz;
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gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
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gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
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for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
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for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
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begin
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begin
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tdi_pad_i<=#1 1'b0;
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gen_clk(1);
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gen_clk(1);
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end
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end
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tdi_pad_i<=#1 crc[i]; // last crc
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tms_pad_i<=#1 1;
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tms_pad_i<=#1 1;
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gen_clk(1); // to exit1_dr
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gen_clk(1); // to exit1_dr
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tdi_pad_i<=#1 'hz; // tri-state
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tms_pad_i<=#1 1;
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tms_pad_i<=#1 1;
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gen_clk(1); // to update_dr
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gen_clk(1); // to update_dr
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tms_pad_i<=#1 0;
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tms_pad_i<=#1 0;
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gen_clk(1); // to run_test_idle
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gen_clk(1); // to run_test_idle
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end
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end
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| Line 823... |
Line 821... |
begin
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begin
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tdi_pad_i<=#1 crc[i];
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tdi_pad_i<=#1 crc[i];
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gen_clk(1);
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gen_clk(1);
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end
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end
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tdi_pad_i<=#1 1'hz;
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if ((last_wb_cmd == `WB_READ8) | (last_wb_cmd == `WB_READ16) | (last_wb_cmd == `WB_READ32)) // When WB_WRITEx was previously activated, data needs to be shifted.
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if ((last_wb_cmd == `WB_READ8) | (last_wb_cmd == `WB_READ16) | (last_wb_cmd == `WB_READ32)) // When WB_WRITEx was previously activated, data needs to be shifted.
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begin
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begin
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$display("\t\tGenerating %0d clocks to read %0d data bytes.", dbg_tb.i_dbg_top.i_dbg_wb.len << 3, dbg_tb.i_dbg_top.i_dbg_wb.len);
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$display("\t\tGenerating %0d clocks to read %0d data bytes.", dbg_tb.i_dbg_top.i_dbg_wb.len << 3, dbg_tb.i_dbg_top.i_dbg_wb.len);
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for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.len << 3); i=i+1)
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for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.len << 3); i=i+1)
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begin
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tdi_pad_i<=#1 1'hz;
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gen_clk(1);
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gen_clk(1);
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end
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end
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end
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gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
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gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
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for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
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for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
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begin
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begin
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tdi_pad_i<=#1 1'b0;
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gen_clk(1);
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gen_clk(1);
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end
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end
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tdi_pad_i<=#1 crc[i]; // last crc
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tms_pad_i<=#1 1;
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tms_pad_i<=#1 1;
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gen_clk(1); // to exit1_dr
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gen_clk(1); // to exit1_dr
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tdi_pad_i<=#1 'hz; // tri-state
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tms_pad_i<=#1 1;
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tms_pad_i<=#1 1;
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gen_clk(1); // to update_dr
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gen_clk(1); // to update_dr
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tms_pad_i<=#1 0;
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tms_pad_i<=#1 0;
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gen_clk(1); // to run_test_idle
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gen_clk(1); // to run_test_idle
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end
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end
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