| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2004/01/22 13:58:53 mohor
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// Port signals are all set to zero after reset.
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//
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// Revision 1.5 2004/01/19 07:32:41 simons
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// Revision 1.5 2004/01/19 07:32:41 simons
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// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
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// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
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//
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//
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// Revision 1.4 2004/01/17 18:38:11 mohor
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// Revision 1.4 2004/01/17 18:38:11 mohor
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// cpu_tall_o is set with cpu_stb_o or register.
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// cpu_tall_o is set with cpu_stb_o or register.
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| Line 273... |
Line 276... |
crc_cnt <= #1 6'h0;
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crc_cnt <= #1 6'h0;
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end
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end
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// Upper limit. Address/length counter counts until this value is reached
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// Upper limit. Address/length counter counts until this value is reached
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always @ (posedge tck_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (cmd_cnt == 2'h2)
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if (rst_i)
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addr_cnt_limit = 6'd0;
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else if (cmd_cnt == 2'h2)
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begin
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begin
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if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO)
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if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO)
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addr_cnt_limit = 6'd0;
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addr_cnt_limit = 6'd0;
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else // (current command is WB_WRITEx or WB_READx)
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else // (current command is WB_WRITEx or WB_READx)
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addr_cnt_limit = 6'd32;
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addr_cnt_limit = 6'd32;
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| Line 291... |
Line 296... |
assign addr_cnt_end = addr_cnt == addr_cnt_limit;
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assign addr_cnt_end = addr_cnt == addr_cnt_limit;
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assign crc_cnt_end = crc_cnt == 6'd32;
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assign crc_cnt_end = crc_cnt == 6'd32;
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assign crc_cnt_31 = crc_cnt == 6'd31;
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assign crc_cnt_31 = crc_cnt == 6'd31;
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assign data_cnt_end = (data_cnt == data_cnt_limit);
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assign data_cnt_end = (data_cnt == data_cnt_limit);
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always @ (posedge tck_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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begin
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crc_cnt_end_q <= #1 1'b0;
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cmd_cnt_end_q <= #1 1'b0;
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data_cnt_end_q <= #1 1'b0;
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end
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else
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begin
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begin
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crc_cnt_end_q <= #1 crc_cnt_end;
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crc_cnt_end_q <= #1 crc_cnt_end;
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cmd_cnt_end_q <= #1 cmd_cnt_end;
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cmd_cnt_end_q <= #1 cmd_cnt_end;
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data_cnt_end_q <= #1 data_cnt_end;
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data_cnt_end_q <= #1 data_cnt_end;
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end
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end
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end
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// Status counter is made of 4 serialy connected registers
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// Status counter is made of 4 serialy connected registers
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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| Line 385... |
Line 399... |
assign dr_write_cpu32 = dr[2:0] == `CPU_WRITE32;
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assign dr_write_cpu32 = dr[2:0] == `CPU_WRITE32;
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assign dr_go = dr[2:0] == `CPU_GO;
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assign dr_go = dr[2:0] == `CPU_GO;
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// Latching instruction
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// Latching instruction
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always @ (posedge tck_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (update_dr_i)
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if (rst_i)
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begin
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dr_read_reg_latched <= #1 1'b0;
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dr_read_cpu8_latched <= #1 1'b0;
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dr_read_cpu32_latched <= #1 1'b0;
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dr_write_reg_latched <= #1 1'b0;
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dr_write_cpu8_latched <= #1 1'b0;
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dr_write_cpu32_latched <= #1 1'b0;
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dr_go_latched <= #1 1'b0;
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end
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else if (update_dr_i)
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begin
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begin
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dr_read_reg_latched <= #1 1'b0;
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dr_read_reg_latched <= #1 1'b0;
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dr_read_cpu8_latched <= #1 1'b0;
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dr_read_cpu8_latched <= #1 1'b0;
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dr_read_cpu32_latched <= #1 1'b0;
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dr_read_cpu32_latched <= #1 1'b0;
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dr_write_reg_latched <= #1 1'b0;
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dr_write_reg_latched <= #1 1'b0;
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| Line 449... |
Line 473... |
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assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);
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assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);
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always @ (posedge tck_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (update_dr_i)
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if (rst_i)
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read_cycle_reg <= #1 1'b0;
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else if (update_dr_i)
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read_cycle_reg <= #1 1'b0;
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read_cycle_reg <= #1 1'b0;
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else if (cmd_read_reg & go_prelim)
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else if (cmd_read_reg & go_prelim)
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read_cycle_reg <= #1 1'b1;
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read_cycle_reg <= #1 1'b1;
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end
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end
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always @ (posedge tck_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (update_dr_i)
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if (rst_i)
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read_cycle_cpu <= #1 1'b0;
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else if (update_dr_i)
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read_cycle_cpu <= #1 1'b0;
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read_cycle_cpu <= #1 1'b0;
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else if (cmd_read_cpu & go_prelim)
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else if (cmd_read_cpu & go_prelim)
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read_cycle_cpu <= #1 1'b1;
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read_cycle_cpu <= #1 1'b1;
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end
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end
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always @ (posedge tck_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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begin
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read_cycle_reg_q <= #1 1'b0;
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read_cycle_cpu_q <= #1 1'b0;
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end
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else
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begin
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begin
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read_cycle_reg_q <= #1 read_cycle_reg;
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read_cycle_reg_q <= #1 read_cycle_reg;
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read_cycle_cpu_q <= #1 read_cycle_cpu;
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read_cycle_cpu_q <= #1 read_cycle_cpu;
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end
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end
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end
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always @ (posedge tck_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (update_dr_i)
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if (rst_i)
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write_cycle_reg <= #1 1'b0;
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else if (update_dr_i)
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write_cycle_reg <= #1 1'b0;
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write_cycle_reg <= #1 1'b0;
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else if (cmd_write_reg & go_prelim)
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else if (cmd_write_reg & go_prelim)
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write_cycle_reg <= #1 1'b1;
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write_cycle_reg <= #1 1'b1;
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end
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end
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| Line 500... |
Line 538... |
assign write_cycle = write_cycle_reg | write_cycle_cpu;
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assign write_cycle = write_cycle_reg | write_cycle_cpu;
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// Start register access cycle
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// Start register access cycle
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always @ (posedge tck_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (write_cycle_reg & data_cnt_end & (~data_cnt_end_q) | read_cycle_reg & (~read_cycle_reg_q))
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begin
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begin
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if (rst_i)
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reg_access <= #1 1'b0;
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else if (write_cycle_reg & data_cnt_end & (~data_cnt_end_q) | read_cycle_reg & (~read_cycle_reg_q))
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reg_access <= #1 1'b1;
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reg_access <= #1 1'b1;
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end
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else
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else
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reg_access <= #1 1'b0;
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reg_access <= #1 1'b0;
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end
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end
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| Line 539... |
Line 577... |
assign cpu_stall_o = cpu_stb_o | cpu_stall_tmp;
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assign cpu_stall_o = cpu_stb_o | cpu_stall_tmp;
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// Synchronizing ack signal from cpu
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// Synchronizing ack signal from cpu
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always @ (posedge tck_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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begin
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cpu_ack_sync <= #1 1'b0;
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cpu_ack_tck <= #1 1'b0;
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cpu_ack_tck_q <= #1 1'b0;
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end
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else
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begin
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begin
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cpu_ack_sync <= #1 cpu_ack_i;
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cpu_ack_sync <= #1 cpu_ack_i;
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cpu_ack_tck <= #1 cpu_ack_sync;
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cpu_ack_tck <= #1 cpu_ack_sync;
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cpu_ack_tck_q <= #1 cpu_ack_tck;
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cpu_ack_tck_q <= #1 cpu_ack_tck;
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end
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end
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end
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// Start cpu access cycle
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// Start cpu access cycle
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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| Line 562... |
Line 609... |
end
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end
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// Synchronizing cpu_stb to cpu_clk_i clock
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// Synchronizing cpu_stb to cpu_clk_i clock
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always @ (posedge cpu_clk_i)
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always @ (posedge cpu_clk_i or posedge rst_i)
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begin
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if (rst_i)
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begin
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cpu_stb_sync <= #1 1'b0;
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cpu_stb_o <= #1 1'b0;
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end
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else
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begin
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begin
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cpu_stb_sync <= #1 cpu_stb;
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cpu_stb_sync <= #1 cpu_stb;
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cpu_stb_o <= #1 cpu_stb_sync;
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cpu_stb_o <= #1 cpu_stb_sync;
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end
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end
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end
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// Latching crc
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// Latching crc
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always @ (posedge tck_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if(crc_cnt_end & (~crc_cnt_end_q))
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if (rst_i)
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crc_match_reg <= #1 1'b0;
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else if(crc_cnt_end & (~crc_cnt_end_q))
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crc_match_reg <= #1 crc_match_i;
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crc_match_reg <= #1 crc_match_i;
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end
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end
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// Status register
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// Status register
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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begin
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status <= #1 4'h0;
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status <= #1 4'h0;
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end
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else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
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else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
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begin
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status <= #1 {crc_match_i, 1'b0, 1'b1, 1'b0};
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status <= #1 {crc_match_i, 1'b0, 1'b1, 1'b0};
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end
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else if (data_cnt_end & (~data_cnt_end_q) & read_cycle)
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else if (data_cnt_end & (~data_cnt_end_q) & read_cycle)
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begin
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status <= #1 {crc_match_reg, 1'b0, 1'b1, 1'b0};
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status <= #1 {crc_match_reg, 1'b0, 1'b1, 1'b0};
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end
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else if (shift_dr_i & (~status_cnt_end))
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else if (shift_dr_i & (~status_cnt_end))
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begin
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status <= #1 {status[0], status[3:1]};
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status <= #1 {status[0], status[3:1]};
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end
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end
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end
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// Following status is shifted out:
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// Following status is shifted out:
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// 1. bit: 1 if crc is OK, else 0
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// 1. bit: 1 if crc is OK, else 0
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// 2. bit: 1'b0
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// 2. bit: 1'b0
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// 3. bit: 1'b1
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// 3. bit: 1'b1
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// 4. bit: 1'b0
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// 4. bit: 1'b0
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