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https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2002/05/07 14:43:59 mohor
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// mon_cntl_o signals that controls monitor mux added.
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//
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// Revision 1.8 2002/01/25 07:58:34 mohor
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// Revision 1.8 2002/01/25 07:58:34 mohor
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// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
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// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
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// not filled-in. Tested in hw.
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// not filled-in. Tested in hw.
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//
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//
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// Revision 1.7 2001/12/06 10:08:06 mohor
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// Revision 1.7 2001/12/06 10:08:06 mohor
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// Enable TRACE
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// Enable TRACE
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//`define TRACE_ENABLED // Uncomment this define to activate the trace
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//`define TRACE_ENABLED // Uncomment this define to activate the trace
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// Define number of cpus supported by the dbg interface
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`define RISC_NUM 8
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// Define IDCODE Value
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// Define IDCODE Value
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`define IDCODE_VALUE 32'hdeadbeef
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`define IDCODE_VALUE 32'hdeadbeef
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// Define master clock (RISC clock)
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// Define master clock (RISC clock)
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Line 156... |
`define MODER_ADR 5'h00
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`define MODER_ADR 5'h00
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`define TSEL_ADR 5'h01
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`define TSEL_ADR 5'h01
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`define QSEL_ADR 5'h02
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`define QSEL_ADR 5'h02
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`define SSEL_ADR 5'h03
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`define SSEL_ADR 5'h03
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`define RISCOP_ADR 5'h04
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`define RISCOP_ADR 5'h04
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`define RISCSEL_ADR 5'h05
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`define RECSEL_ADR 5'h10
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`define RECSEL_ADR 5'h10
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`define MON_CNTL_ADR 5'h11
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`define MON_CNTL_ADR 5'h11
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// Registers default values (after reset)
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// Registers default values (after reset)
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