URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [highland_ver1/] [rtl/] [verilog/] [dbg_defines.v] - Diff between revs 47 and 57

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Rev 47	Rev 57
Line 43...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.9 2002/05/07 14:43:59 mohor`
	`// mon_cntl_o signals that controls monitor mux added.`
	`//`
`// Revision 1.8 2002/01/25 07:58:34 mohor`	`// Revision 1.8 2002/01/25 07:58:34 mohor`
`// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in`	`// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in`
`// not filled-in. Tested in hw.`	`// not filled-in. Tested in hw.`
`//`	`//`
`// Revision 1.7 2001/12/06 10:08:06 mohor`	`// Revision 1.7 2001/12/06 10:08:06 mohor`
Line 85...	Line 88...


`// Enable TRACE`	`// Enable TRACE`
//`define TRACE_ENABLED // Uncomment this define to activate the trace	//`define TRACE_ENABLED // Uncomment this define to activate the trace

	`// Define number of cpus supported by the dbg interface`
	`define RISC_NUM 8

`// Define IDCODE Value`	`// Define IDCODE Value`
`define IDCODE_VALUE 32'hdeadbeef	`define IDCODE_VALUE 32'hdeadbeef

`// Define master clock (RISC clock)`	`// Define master clock (RISC clock)`
Line 151...	Line 156...
`define MODER_ADR 5'h00	`define MODER_ADR 5'h00
`define TSEL_ADR 5'h01	`define TSEL_ADR 5'h01
`define QSEL_ADR 5'h02	`define QSEL_ADR 5'h02
`define SSEL_ADR 5'h03	`define SSEL_ADR 5'h03
`define RISCOP_ADR 5'h04	`define RISCOP_ADR 5'h04
	`define RISCSEL_ADR 5'h05
`define RECSEL_ADR 5'h10	`define RECSEL_ADR 5'h10
`define MON_CNTL_ADR 5'h11	`define MON_CNTL_ADR 5'h11


`// Registers default values (after reset)`	`// Registers default values (after reset)`

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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [highland_ver1/] [rtl/] [verilog/] [dbg_defines.v] - Diff between revs 47 and 57