| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2004/01/07 11:58:56 mohor
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// temp4 version.
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//
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// Revision 1.5 2004/01/06 17:15:19 mohor
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// Revision 1.5 2004/01/06 17:15:19 mohor
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// temp3 version.
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// temp3 version.
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//
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//
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// Revision 1.4 2004/01/05 12:16:00 mohor
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// Revision 1.4 2004/01/05 12:16:00 mohor
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// tmp2 version.
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// tmp2 version.
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| Line 130... |
Line 133... |
reg wb_cyc_o;
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reg wb_cyc_o;
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reg [31:0] wb_adr_o;
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reg [31:0] wb_adr_o;
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reg [31:0] wb_dat_o;
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reg [31:0] wb_dat_o;
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reg [3:0] wb_sel_o;
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reg [3:0] wb_sel_o;
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reg [3:0] wb_sel_old;
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reg tdo_o;
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reg tdo_o;
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reg [50:0] dr;
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reg [50:0] dr;
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wire enable;
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wire enable;
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wire cmd_cnt_en;
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reg [1:0] cmd_cnt;
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reg [1:0] cmd_cnt;
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wire cmd_cnt_end;
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wire cmd_cnt_end;
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reg cmd_cnt_end_q;
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reg cmd_cnt_end_q;
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wire addr_len_cnt_en;
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reg [5:0] addr_len_cnt;
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reg [5:0] addr_len_cnt;
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reg [5:0] addr_len_cnt_limit;
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reg [5:0] addr_len_cnt_limit;
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wire addr_len_cnt_end;
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wire addr_len_cnt_end;
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wire crc_cnt_en;
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reg [5:0] crc_cnt;
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reg [5:0] crc_cnt;
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wire crc_cnt_end;
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wire crc_cnt_end;
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reg crc_cnt_end_q;
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reg crc_cnt_end_q;
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wire data_cnt_en;
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reg [18:0] data_cnt;
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reg [18:0] data_cnt;
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reg [18:0] data_cnt_limit;
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reg [18:0] data_cnt_limit;
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wire data_cnt_end;
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wire data_cnt_end;
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reg data_cnt_end_q;
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reg status_reset_en;
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reg status_reset_en;
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reg crc_match_reg;
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reg [`STATUS_CNT -1:0] status_cnt;
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// reg [31:0] data_tck;
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reg [2:0] cmd, cmd_old;
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reg [2:0] cmd, cmd_old;
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reg [31:0] adr;
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reg [31:0] adr;
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reg [15:0] len;
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reg [15:0] len;
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reg start_rd_tck;
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reg start_rd_tck;
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| Line 165... |
Line 171... |
reg start_wr_tck;
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reg start_wr_tck;
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reg start_wr_sync1;
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reg start_wr_sync1;
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reg start_wb_wr;
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reg start_wb_wr;
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reg start_wb_wr_q;
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reg start_wb_wr_q;
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reg cmd_write;
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reg dr_write_latched;
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reg cmd_read;
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reg dr_read_latched;
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reg cmd_go;
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reg dr_go_latched;
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wire status_cnt_end;
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wire status_cnt_end;
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wire byte, half, long;
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wire byte, half, long;
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reg byte_q, half_q, long_q;
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reg byte_q, half_q, long_q;
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//wire previous_cmd_read;
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wire cmd_read;
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wire previous_cmd_write;
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wire cmd_write;
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wire cmd_go;
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wire cmd_old_read;
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reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;
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|
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assign enable = wishbone_ce_i & shift_dr_i;
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assign enable = wishbone_ce_i & shift_dr_i;
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assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end); // igor !!! Add something so CRC is calculated when data is read from WB
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assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
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assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
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assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
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//always @ (posedge tck_i)
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//begin
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// if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
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// dr <= #1 {dr[49:0], tdi_i};
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//end
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
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/* if (cmd_old_read & cmd_go)
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begin
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case (cmd_old) // synthesis parallel_case full_case
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`WB_READ8 : begin
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if(byte & (~byte_q))
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dr[31:24] <= #1 input_data[]; mama
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else
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dr <= #1 dr<<1;
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end
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`WB_READ16: begin
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if(half & (~half_q))
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start_rd_tck <= #1 1'b1;
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else
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start_rd_tck <= #1 1'b0;
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end
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`WB_READ32: begin
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if(long & (~long_q))
|
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start_rd_tck <= #1 1'b1;
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else
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start_rd_tck <= #1 1'b0;
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end
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endcase
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end
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else*/ if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
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dr <= #1 {dr[49:0], tdi_i};
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dr <= #1 {dr[49:0], tdi_i};
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end
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end
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//always @ (posedge tck_i)
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assign cmd_cnt_en = enable & (~cmd_cnt_end);
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//begin
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// if (enable & (data_cnt_end)) // Igor !!! perhaps not needed data_cnt_end
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// data_tck <= #1 {data_tck[30:0], tdi_i};
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//end
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always @ (posedge tck_i or posedge trst_i)
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always @ (posedge tck_i or posedge trst_i)
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begin
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begin
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if (trst_i)
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if (trst_i)
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cmd_cnt <= #1 'h0;
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cmd_cnt <= #1 'h0;
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else if (update_dr_i)
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else if (update_dr_i)
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cmd_cnt <= #1 'h0;
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cmd_cnt <= #1 'h0;
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else if (enable & (~cmd_cnt_end))
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else if (cmd_cnt_en)
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cmd_cnt <= #1 cmd_cnt + 1'b1;
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cmd_cnt <= #1 cmd_cnt + 1'b1;
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end
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end
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assign addr_len_cnt_en = enable & cmd_cnt_end & (~addr_len_cnt_end);
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always @ (posedge tck_i or posedge trst_i)
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always @ (posedge tck_i or posedge trst_i)
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begin
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begin
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if (trst_i)
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if (trst_i)
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addr_len_cnt <= #1 'h0;
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addr_len_cnt <= #1 'h0;
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else if (update_dr_i)
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else if (update_dr_i)
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addr_len_cnt <= #1 'h0;
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addr_len_cnt <= #1 'h0;
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else if (enable & cmd_cnt_end & (~addr_len_cnt_end))
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else if (addr_len_cnt_en)
|
addr_len_cnt <= #1 addr_len_cnt + 1'b1;
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addr_len_cnt <= #1 addr_len_cnt + 1'b1;
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end
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end
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assign data_cnt_en = enable & cmd_cnt_end & (~data_cnt_end);
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|
always @ (posedge tck_i or posedge trst_i)
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always @ (posedge tck_i or posedge trst_i)
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begin
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begin
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if (trst_i)
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if (trst_i)
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data_cnt <= #1 'h0;
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data_cnt <= #1 'h0;
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else if (update_dr_i)
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else if (update_dr_i)
|
data_cnt <= #1 'h0;
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data_cnt <= #1 'h0;
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// else if (enable & cmd_cnt_end & (~data_cnt_end)) // igor !!! add something that will count output data
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else if (data_cnt_en)
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else if (enable & (~data_cnt_end) & cmd_go & ((cmd_cnt_end & previous_cmd_write | crc_cnt_end & cmd_read)))
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data_cnt <= #1 data_cnt + 1'b1;
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data_cnt <= #1 data_cnt + 1'b1;
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end
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end
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| Line 244... |
Line 283... |
long_q <= #1 long;
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long_q <= #1 long;
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end
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end
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//assign previous_cmd_read = (cmd == `WB_READ8) | (cmd == `WB_READ16) | (cmd == `WB_READ32);
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assign cmd_read = (cmd == `WB_READ8) | (cmd == `WB_READ16) | (cmd == `WB_READ32);
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assign previous_cmd_write = (cmd == `WB_WRITE8) | (cmd == `WB_WRITE16) | (cmd == `WB_WRITE32);
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assign cmd_write = (cmd == `WB_WRITE8) | (cmd == `WB_WRITE16) | (cmd == `WB_WRITE32);
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assign cmd_go = cmd == `WB_GO;
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assign cmd_old_read = (cmd_old == `WB_READ8) | (cmd_old == `WB_READ16) | (cmd_old == `WB_READ32);
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wire dr_read;
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wire dr_read;
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wire dr_write;
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wire dr_write;
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wire dr_go;
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wire dr_go;
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wire dr_status;
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wire dr_status;
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| Line 261... |
Line 303... |
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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if (update_dr_i)
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if (update_dr_i)
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cmd_read <= #1 1'b0;
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dr_read_latched <= #1 1'b0;
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else if (cmd_cnt_end & (~cmd_cnt_end_q))
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else if (cmd_cnt_end & (~cmd_cnt_end_q))
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cmd_read <= #1 dr_read;
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dr_read_latched <= #1 dr_read;
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end
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end
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|
|
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
|
if (update_dr_i)
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if (update_dr_i)
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cmd_write <= #1 1'b0;
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dr_write_latched <= #1 1'b0;
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else if (cmd_cnt_end & (~cmd_cnt_end_q))
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else if (cmd_cnt_end & (~cmd_cnt_end_q))
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cmd_write <= #1 dr_write;
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dr_write_latched <= #1 dr_write;
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end
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end
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|
|
|
|
always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
|
if (update_dr_i)
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if (update_dr_i)
|
cmd_go <= #1 1'b0;
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dr_go_latched <= #1 1'b0;
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else if (cmd_cnt_end & (~cmd_cnt_end_q))
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else if (cmd_cnt_end & (~cmd_cnt_end_q))
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cmd_go <= #1 dr_go;
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dr_go_latched <= #1 dr_go;
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end
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end
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|
|
|
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|
|
always @ (posedge tck_i)
|
|
|
always @ (cmd_cnt_end or cmd_cnt_end_q or dr)
|
|
begin
|
begin
|
if (cmd_cnt_end & (~cmd_cnt_end_q))
|
if (cmd_cnt == 2'h2)
|
begin
|
begin
|
// (current command is WB_STATUS or WB_GO)
|
if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO)
|
if (dr_status | dr_go)
|
|
addr_len_cnt_limit = 6'd0;
|
addr_len_cnt_limit = 6'd0;
|
// (current command is WB_WRITEx or WB_READx)
|
else // (current command is WB_WRITEx or WB_READx)
|
else
|
|
addr_len_cnt_limit = 6'd48;
|
addr_len_cnt_limit = 6'd48;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
always @ (cmd_cnt_end or cmd_cnt_end_q or dr or previous_cmd_write or len)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (cmd_cnt_end & (~cmd_cnt_end_q))
|
if (cmd_cnt == 2'h2)
|
|
begin
|
|
if (dr[1] & (~dr[0]) & (~tdi_i) & cmd_write) // current command is WB_GO and previous command is WB_WRITEx)
|
|
data_cnt_limit = (len<<3);
|
|
else
|
|
data_cnt_limit = 19'h0;
|
|
end
|
|
else if (crc_cnt == 6'd31)
|
begin
|
begin
|
// (current command is WB_GO and previous command is WB_WRITEx)
|
if (dr_go_latched & cmd_read) // current command is WB_GO and previous command is WB_READx)
|
if (dr_go & previous_cmd_write)
|
|
data_cnt_limit = (len<<3);
|
data_cnt_limit = (len<<3);
|
else
|
else
|
data_cnt_limit = 19'h0;
|
data_cnt_limit = 19'h0;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
assign crc_cnt_en = enable & cmd_cnt_end & addr_len_cnt_end & data_cnt_end & (~crc_cnt_end);
|
|
|
// crc counter
|
// crc counter
|
always @ (posedge tck_i or posedge trst_i)
|
always @ (posedge tck_i or posedge trst_i)
|
begin
|
begin
|
if (trst_i)
|
if (trst_i)
|
crc_cnt <= #1 'h0;
|
crc_cnt <= #1 'h0;
|
// else if(enable & addr_len_cnt_end & (~crc_cnt_end))
|
else if(crc_cnt_en)
|
else if(enable & cmd_cnt_end & addr_len_cnt_end & data_cnt_end & (~crc_cnt_end))
|
|
crc_cnt <= #1 crc_cnt + 1'b1;
|
crc_cnt <= #1 crc_cnt + 1'b1;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
crc_cnt <= #1 'h0;
|
crc_cnt <= #1 'h0;
|
end
|
end
|
|
|
assign cmd_cnt_end = cmd_cnt == 2'h3;
|
assign cmd_cnt_end = cmd_cnt == 2'h3;
|
//assign addr_len_cnt_end = addr_len_cnt == 6'd48;
|
|
assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
|
assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
|
assign crc_cnt_end = crc_cnt == 6'd32;
|
assign crc_cnt_end = crc_cnt == 6'd32;
|
assign data_cnt_end = (data_cnt == data_cnt_limit);
|
assign data_cnt_end = (data_cnt == data_cnt_limit);
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
crc_cnt_end_q <= #1 crc_cnt_end;
|
crc_cnt_end_q <= #1 crc_cnt_end;
|
cmd_cnt_end_q <= #1 cmd_cnt_end;
|
cmd_cnt_end_q <= #1 cmd_cnt_end;
|
|
data_cnt_end_q <= #1 data_cnt_end;
|
|
end
|
|
|
|
|
|
|
|
always @ (posedge tck_i or posedge trst_i)
|
|
begin
|
|
if (trst_i)
|
|
status_cnt1 <= #1 1'b0;
|
|
else if (update_dr_i)
|
|
status_cnt1 <= #1 1'b0;
|
|
else if (data_cnt_end & (~data_cnt_end_q) & cmd_old_read & dr_go_latched |
|
|
crc_cnt_end & (~crc_cnt_end_q) & (~(cmd_read & dr_go_latched)) // cmd is not changed, yet.
|
|
)
|
|
status_cnt1 <= #1 1'b1;
|
end
|
end
|
|
|
// status counter
|
|
always @ (posedge tck_i or posedge trst_i)
|
always @ (posedge tck_i or posedge trst_i)
|
begin
|
begin
|
if (trst_i)
|
if (trst_i)
|
status_cnt <= #1 'h0;
|
begin
|
else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
|
status_cnt2 <= #1 1'b0;
|
status_cnt <= #1 status_cnt + 1'b1;
|
status_cnt3 <= #1 1'b0;
|
|
status_cnt4 <= #1 1'b0;
|
|
end
|
else if (update_dr_i)
|
else if (update_dr_i)
|
status_cnt <= #1 'h0;
|
begin
|
|
status_cnt2 <= #1 1'b0;
|
|
status_cnt3 <= #1 1'b0;
|
|
status_cnt4 <= #1 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
status_cnt2 <= #1 status_cnt1;
|
|
status_cnt3 <= #1 status_cnt2;
|
|
status_cnt4 <= #1 status_cnt3;
|
end
|
end
|
|
end
|
|
|
|
|
assign status_cnt_end = status_cnt == `STATUS_LEN;
|
|
|
|
|
|
|
assign status_cnt_end = status_cnt4;
|
reg [`STATUS_LEN -1:0] status;
|
reg [`STATUS_LEN -1:0] status;
|
//reg address_unaligned;
|
|
|
|
reg wb_error, wb_error_sync, wb_error_tck;
|
reg wb_error, wb_error_sync, wb_error_tck;
|
reg wb_overrun, wb_overrun_sync, wb_overrun_tck;
|
reg wb_overrun, wb_overrun_sync, wb_overrun_tck;
|
|
|
reg busy_wb;
|
reg busy_wb;
|
| Line 369... |
Line 442... |
reg wb_end_sync;
|
reg wb_end_sync;
|
reg wb_end_tck;
|
reg wb_end_tck;
|
reg busy_sync;
|
reg busy_sync;
|
reg [799:0] TDO_WISHBONE;
|
reg [799:0] TDO_WISHBONE;
|
|
|
|
|
|
|
always @ (posedge tck_i or posedge trst_i)
|
always @ (posedge tck_i or posedge trst_i)
|
begin
|
begin
|
if (trst_i)
|
if (trst_i)
|
status <= #1 'h0;
|
status <= #1 'h0;
|
else if(crc_cnt_end & (~crc_cnt_end_q))
|
else if(crc_cnt_end & (~crc_cnt_end_q) & (~dr_read_latched))
|
status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,
|
status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,
|
|
else if (data_cnt_end & (~data_cnt_end_q) & dr_read_latched)
|
|
status <= #1 {crc_match_reg, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,
|
else if (shift_dr_i & (~status_cnt_end))
|
else if (shift_dr_i & (~status_cnt_end))
|
status <= #1 {status[0], status[`STATUS_LEN -1:1]};
|
status <= #1 {status[0], status[`STATUS_LEN -1:1]};
|
end
|
end
|
// Following status is shifted out:
|
// Following status is shifted out:
|
// 1. bit: 1 if crc is OK, else 0
|
// 1. bit: 1 if crc is OK, else 0
|
| Line 386... |
Line 463... |
// 3. bit: 1 if overrun occured during write (data couldn't be written fast enough)
|
// 3. bit: 1 if overrun occured during write (data couldn't be written fast enough)
|
// 4. bit: 1 if WB error occured, else 0
|
// 4. bit: 1 if WB error occured, else 0
|
|
|
|
|
|
|
always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck)
|
always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck or cmd_read or data_cnt_end or data_cnt_end_q or crc_match_reg or dr_read_latched)
|
begin
|
begin
|
if (pause_dr_i)
|
if (pause_dr_i)
|
begin
|
begin
|
tdo_o = busy_tck;
|
tdo_o = busy_tck;
|
TDO_WISHBONE = "busy_tck";
|
TDO_WISHBONE = "busy_tck";
|
end
|
end
|
else if (crc_cnt_end & (~crc_cnt_end_q))
|
else if (crc_cnt_end & (~crc_cnt_end_q) & (~(dr_go_latched & cmd_read))) // cmd is updated not updated, yet
|
begin
|
begin
|
tdo_o = crc_match_i;
|
tdo_o = crc_match_i;
|
TDO_WISHBONE = "crc_match_i";
|
TDO_WISHBONE = "crc_match_i";
|
end
|
end
|
else if (crc_cnt_end)
|
else if (data_cnt_end & (~data_cnt_end_q) & dr_go_latched & cmd_old_read) // cmd is already updated
|
|
begin
|
|
tdo_o = crc_match_reg;
|
|
TDO_WISHBONE = "crc_match_reg";
|
|
end
|
|
else if (crc_cnt_end & (~(dr_go_latched & cmd_old_read)) | data_cnt_end & dr_go_latched & cmd_old_read) // cmd is already updated
|
begin
|
begin
|
tdo_o = status[0];
|
tdo_o = status[0];
|
TDO_WISHBONE = "status";
|
TDO_WISHBONE = "status";
|
end
|
end
|
else
|
else
|
| Line 415... |
Line 497... |
|
|
reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
|
reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
if(crc_cnt_end & (~crc_cnt_end_q))
|
|
crc_match_reg <= #1 crc_match_i;
|
|
end
|
|
|
|
|
|
always @ (posedge tck_i or posedge trst_i)
|
begin
|
begin
|
if (cmd_write | cmd_read)
|
if (trst_i)
|
begin
|
begin
|
cmd <= #1 dr[50:48];
|
cmd <= #1 'h0;
|
adr <= #1 dr[47:16];
|
cmd_old <= #1 'h0;
|
len <= #1 dr[15:0];
|
|
set_addr <= #1 1'b1;
|
|
end
|
end
|
else
|
else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
begin
|
begin
|
|
if (dr_write_latched | dr_read_latched)
|
|
cmd <= #1 dr[50:48];
|
|
else
|
cmd <= #1 dr[2:0];
|
cmd <= #1 dr[2:0];
|
end
|
|
|
|
cmd_old <= #1 cmd;
|
cmd_old <= #1 cmd;
|
end
|
end
|
|
end
|
|
|
|
|
|
always @ (posedge tck_i)
|
|
begin
|
|
if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
|
begin
|
|
if (dr_write_latched | dr_read_latched)
|
|
begin
|
|
adr <= #1 dr[47:16];
|
|
len <= #1 dr[15:0];
|
|
set_addr <= #1 1'b1;
|
|
end
|
|
end
|
else
|
else
|
set_addr <= #1 1'b0;
|
set_addr <= #1 1'b0;
|
end
|
end
|
|
|
|
|
// Start wishbone read cycle
|
// Start wishbone read cycle
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (set_addr & cmd_read)
|
if (set_addr & dr_read_latched)
|
|
start_rd_tck <= #1 1'b1;
|
|
else if (cmd_old_read & cmd_go & crc_cnt_end_q & (~data_cnt_end))
|
|
begin
|
|
case (cmd_old) // synthesis parallel_case full_case
|
|
`WB_READ8 : begin
|
|
if(byte & (~byte_q))
|
|
start_rd_tck <= #1 1'b1;
|
|
else
|
|
start_rd_tck <= #1 1'b0;
|
|
end
|
|
`WB_READ16: begin
|
|
if(half & (~half_q))
|
start_rd_tck <= #1 1'b1;
|
start_rd_tck <= #1 1'b1;
|
else
|
else
|
start_rd_tck <= #1 1'b0;
|
start_rd_tck <= #1 1'b0;
|
end
|
end
|
|
`WB_READ32: begin
|
|
if(long & (~long_q))
|
|
start_rd_tck <= #1 1'b1;
|
|
else
|
|
start_rd_tck <= #1 1'b0;
|
|
end
|
|
endcase
|
|
end
|
|
else
|
|
start_rd_tck <= #1 1'b0;
|
|
end
|
|
|
|
|
|
|
// Start wishbone write cycle
|
// Start wishbone write cycle
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (cmd_go & previous_cmd_write)
|
if (dr_go_latched & cmd_write)
|
begin
|
begin
|
case (cmd) // synthesis parallel_case full_case
|
case (cmd) // synthesis parallel_case full_case
|
`WB_WRITE8 : begin
|
`WB_WRITE8 : begin
|
if (byte & (~byte_q))
|
if (byte & (~byte_q))
|
begin
|
begin
|
| Line 536... |
Line 660... |
else
|
else
|
wb_adr_o <= #1 wb_adr_o + 3'd4;
|
wb_adr_o <= #1 wb_adr_o + 3'd4;
|
end
|
end
|
end
|
end
|
|
|
`define WB_STATUS 3'h0 // igor !!! Delete this lines
|
|
`define WB_WRITE8 3'h1 // igor !!! Delete this lines
|
|
`define WB_WRITE16 3'h2 // igor !!! Delete this lines
|
|
`define WB_WRITE32 3'h3 // igor !!! Delete this lines
|
|
`define WB_GO 3'h4 // igor !!! Delete this lines
|
|
`define WB_READ8 3'h5 // igor !!! Delete this lines
|
|
`define WB_READ16 3'h6 // igor !!! Delete this lines
|
|
`define WB_READ32 3'h7 // igor !!! Delete this lines
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| Line 574... |
Line 688... |
wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
|
wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
|
end
|
end
|
end
|
end
|
|
|
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
|
begin
|
/*
|
if (wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
wb_sel_old <= #1 4'h0;
|
begin
|
else if (wb_ack_i)
|
if (wb_rst_i)
|
wb_sel_old <= #1 wb_sel_o;
|
wb_dat_o[31:0] <= #1 32'h0;
|
end
|
else if (start_wb_wr & (~start_wb_wr_q))
|
|
begin
|
|
if (cmd[1:0] == 2'd1) // 8-bit access
|
|
wb_dat_o[31:0] <= #1 {4{8'h0}};
|
|
else if (cmd[1:0] == 2'd2) // 16-bit access
|
|
wb_dat_o[31:0] <= #1 {2{16'h0}};
|
|
else
|
|
wb_dat_o[31:0] <= #1 32'h0; //32-bit access
|
|
end
|
|
end
|
|
*/
|
|
|
|
//always @ (wb_adr_o or cmd)
|
|
//begin
|
|
// wb_sel_o[0] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
|
|
// (cmd[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
|
|
// wb_sel_o[1] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1] ^ cmd[0]) & (wb_adr_o[1:0] == 2'b10);
|
|
// wb_sel_o[2] = (cmd[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
|
|
// wb_sel_o[3] = (wb_adr_o[1:0] == 2'b00);
|
|
//end
|
|
|
|
|
|
|
|
// always @ (dr)
|
|
// begin
|
|
// address_unaligned = (dr[1:0] == 2'b11) & (dr[4:3] > 2'b00) | (dr[1:0] == 2'b10) & (dr[3]);
|
|
// end
|
|
|
|
|
|
|
|
assign wb_we_o = ~cmd[2]; // Status or write (for simpler logic status is allowed)
|
assign wb_we_o = ~cmd[2]; // Status or write (for simpler logic status is allowed)
|
assign wb_cab_o = 1'b0;
|
assign wb_cab_o = 1'b0;
|
assign wb_stb_o = wb_cyc_o;
|
assign wb_stb_o = wb_cyc_o;
|
