| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.12 2003/09/17 14:38:57 simons
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// WB_CNTL register added, some syncronization fixes.
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//
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// Revision 1.11 2003/08/28 13:55:21 simons
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// Revision 1.11 2003/08/28 13:55:21 simons
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// Three more chains added for cpu debug access.
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// Three more chains added for cpu debug access.
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//
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//
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// Revision 1.10 2003/07/31 12:19:49 simons
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// Revision 1.10 2003/07/31 12:19:49 simons
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// Multiple cpu support added.
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// Multiple cpu support added.
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| Line 95... |
Line 98... |
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// Enable TRACE
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// Enable TRACE
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//`define TRACE_ENABLED // Uncomment this define to activate the trace
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//`define TRACE_ENABLED // Uncomment this define to activate the trace
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// Define number of cpus supported by the dbg interface
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// Define number of cpus supported by the dbg interface
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`define RISC_NUM 8
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`define RISC_NUM 2
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// Define IDCODE Value
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// Define IDCODE Value
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`define IDCODE_VALUE 32'hdeadbeef
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`define IDCODE_VALUE 32'h14951185
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// Define master clock (RISC clock)
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// Define master clock (RISC clock)
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//`define RISC_CLOCK 50 // Half period = 50 ns => MCLK = 10 Mhz
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//`define RISC_CLOCK 50 // Half period = 50 ns => MCLK = 10 Mhz
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`define RISC_CLOCK 2.5 // Half period = 5 ns => MCLK = 200 Mhz
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`define RISC_CLOCK 2.5 // Half period = 5 ns => MCLK = 200 Mhz
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| Line 127... |
Line 130... |
// OpSelect width
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// OpSelect width
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`define OPSELECTWIDTH 3
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`define OPSELECTWIDTH 3
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`define OPSELECTIONCOUNTER 8 //2^3
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`define OPSELECTIONCOUNTER 8 //2^3
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// OpSelect (dbg_op_i) signal meaning
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// OpSelect (dbg_op_i) signal meaning
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//`define DEBUG_READ_PC 0
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//`define DEBUG_READ_LSEA 1
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//`define DEBUG_READ_LDATA 2
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//`define DEBUG_READ_SDATA 3
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//`define DEBUG_READ_SPR 4
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//`define DEBUG_WRITE_SPR 5
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//`define DEBUG_READ_INSTR 6
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//`define Reserved 7
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`define DEBUG_READ_0 0
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`define DEBUG_READ_0 0
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`define DEBUG_WRITE_0 1
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`define DEBUG_WRITE_0 1
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`define DEBUG_READ_1 2
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`define DEBUG_READ_1 2
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`define DEBUG_WRITE_1 3
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`define DEBUG_WRITE_1 3
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`define DEBUG_READ_2 4
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`define DEBUG_READ_2 4
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| Line 155... |
Line 149... |
`define INTEST 4'b0100
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`define INTEST 4'b0100
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`define CLAMP 4'b0101
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`define CLAMP 4'b0101
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`define CLAMPZ 4'b0110
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`define CLAMPZ 4'b0110
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`define HIGHZ 4'b0111
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`define HIGHZ 4'b0111
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`define DEBUG 4'b1000
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`define DEBUG 4'b1000
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`define MBIST 4'b1001
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`define BYPASS 4'b1111
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`define BYPASS 4'b1111
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// Chains
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// Chains
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`define GLOBAL_BS_CHAIN 4'b0000
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`define GLOBAL_BS_CHAIN 4'b0000
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`define RISC_DEBUG_CHAIN_2 4'b0001
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`define RISC_DEBUG_CHAIN_2 4'b0001
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