| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.13 2003/10/21 09:48:31 simons
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// Mbist support added.
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//
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// Revision 1.12 2003/09/17 14:38:57 simons
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// Revision 1.12 2003/09/17 14:38:57 simons
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// WB_CNTL register added, some syncronization fixes.
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// WB_CNTL register added, some syncronization fixes.
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//
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//
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// Revision 1.11 2003/08/28 13:55:21 simons
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// Revision 1.11 2003/08/28 13:55:21 simons
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// Three more chains added for cpu debug access.
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// Three more chains added for cpu debug access.
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| Line 98... |
Line 101... |
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// Enable TRACE
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// Enable TRACE
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//`define TRACE_ENABLED // Uncomment this define to activate the trace
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//`define TRACE_ENABLED // Uncomment this define to activate the trace
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// Define number of cpus supported by the dbg interface
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// Define number of cpus supported by the dbg interface
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`define RISC_NUM 2
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`define CPU_NUM 2
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// Define IDCODE Value
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// Define IDCODE Value
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`define IDCODE_VALUE 32'h14951185
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`define IDCODE_VALUE 32'h14951185
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// Define master clock (RISC clock)
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// Define master clock (CPU clock)
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//`define RISC_CLOCK 50 // Half period = 50 ns => MCLK = 10 Mhz
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//`define CPU_CLOCK 50 // Half period = 50 ns => MCLK = 10 Mhz
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`define RISC_CLOCK 2.5 // Half period = 5 ns => MCLK = 200 Mhz
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`define CPU_CLOCK 2.5 // Half period = 5 ns => MCLK = 200 Mhz
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// Length of the Instruction register
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// Length of the Instruction register
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`define IR_LENGTH 4
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`define IR_LENGTH 4
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// Length of the Data register (must be equal to the longest scan chain for shifting the data in)
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// Length of the Data register (must be equal to the longest scan chain for shifting the data in)
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| Line 154... |
Line 157... |
`define MBIST 4'b1001
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`define MBIST 4'b1001
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`define BYPASS 4'b1111
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`define BYPASS 4'b1111
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// Chains
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// Chains
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`define GLOBAL_BS_CHAIN 4'b0000
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`define GLOBAL_BS_CHAIN 4'b0000
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`define RISC_DEBUG_CHAIN_2 4'b0001
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`define CPU_DEBUG_CHAIN_2 4'b0001
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`define RISC_TEST_CHAIN 4'b0010
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`define CPU_TEST_CHAIN 4'b0010
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`define TRACE_TEST_CHAIN 4'b0011
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`define TRACE_TEST_CHAIN 4'b0011
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`define REGISTER_SCAN_CHAIN 4'b0100
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`define REGISTER_SCAN_CHAIN 4'b0100
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`define WISHBONE_SCAN_CHAIN 4'b0101
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`define WISHBONE_SCAN_CHAIN 4'b0101
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`define RISC_DEBUG_CHAIN_0 4'b0110
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`define CPU_DEBUG_CHAIN_0 4'b0110
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`define RISC_DEBUG_CHAIN_1 4'b0111
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`define CPU_DEBUG_CHAIN_1 4'b0111
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`define RISC_DEBUG_CHAIN_3 4'b1000
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`define CPU_DEBUG_CHAIN_3 4'b1000
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// Registers addresses
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// Registers addresses
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`define MODER_ADR 5'h00
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`define MODER_ADR 5'h00
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`define TSEL_ADR 5'h01
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`define TSEL_ADR 5'h01
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`define QSEL_ADR 5'h02
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`define QSEL_ADR 5'h02
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`define SSEL_ADR 5'h03
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`define SSEL_ADR 5'h03
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`define RISCOP_ADR 5'h04
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`define CPUOP_ADR 5'h04
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`define RISCSEL_ADR 5'h05
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`define CPUSEL_ADR 5'h05
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`define RECSEL_ADR 5'h10
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`define RECSEL_ADR 5'h10
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`define MON_CNTL_ADR 5'h11
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`define MON_CNTL_ADR 5'h11
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`define WB_CNTL_ADR 5'h12
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`define WB_CNTL_ADR 5'h12
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// Registers default values (after reset)
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// Registers default values (after reset)
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`define MODER_DEF 2'h0
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`define MODER_DEF 2'h0
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`define TSEL_DEF 32'h00000000
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`define TSEL_DEF 32'h00000000
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`define QSEL_DEF 32'h00000000
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`define QSEL_DEF 32'h00000000
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`define SSEL_DEF 32'h00000000
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`define SSEL_DEF 32'h00000000
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`define RISCOP_DEF 2'h0
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`define CPUOP_DEF 2'h0
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`define RECSEL_DEF 7'h0
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`define RECSEL_DEF 7'h0
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`define MON_CNTL_DEF 4'h0
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`define MON_CNTL_DEF 4'h0
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No newline at end of file
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No newline at end of file
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