| Line 10... |
Line 10... |
//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// All additional information is available in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000,2001 Authors ////
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//// Copyright (C) 2000,2001, 2002 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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| Line 43... |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.27 2002/10/10 02:42:55 mohor
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// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.
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//
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// Revision 1.26 2002/05/07 14:43:59 mohor
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// Revision 1.26 2002/05/07 14:43:59 mohor
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// mon_cntl_o signals that controls monitor mux added.
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// mon_cntl_o signals that controls monitor mux added.
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//
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//
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// Revision 1.25 2002/04/22 12:54:11 mohor
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// Revision 1.25 2002/04/22 12:54:11 mohor
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// Signal names changed to lower case.
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// Signal names changed to lower case.
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| Line 347... |
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wire BitCounter_Lt40;
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wire BitCounter_Lt40;
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`endif
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`endif
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assign trst = ~trst_in; // trst_pad_i is active low
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assign trst = trst_in; // trst_pad_i is active high !!! Inverted on higher layer.
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/**********************************************************************************
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/**********************************************************************************
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* *
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* *
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* JTAG_DR: JTAG Data Register *
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* JTAG_DR: JTAG Data Register *
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