| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.29 2003/07/31 12:19:49 simons
|
|
// Multiple cpu support added.
|
|
//
|
// Revision 1.28 2002/11/06 14:22:41 mohor
|
// Revision 1.28 2002/11/06 14:22:41 mohor
|
// Trst signal is not inverted here any more. Inverted on higher layer !!!.
|
// Trst signal is not inverted here any more. Inverted on higher layer !!!.
|
//
|
//
|
// Revision 1.27 2002/10/10 02:42:55 mohor
|
// Revision 1.27 2002/10/10 02:42:55 mohor
|
// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.
|
// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.
|
| Line 245... |
Line 248... |
reg [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
|
reg [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
|
|
|
reg [`CHAIN_ID_LENGTH-1:0] Chain; // Selected chain
|
reg [`CHAIN_ID_LENGTH-1:0] Chain; // Selected chain
|
reg [31:0] DataReadLatch; // Data when reading register or RISC is latched one risc_clk_i clock after the data is read.
|
reg [31:0] DataReadLatch; // Data when reading register or RISC is latched one risc_clk_i clock after the data is read.
|
reg RegAccessTck; // Indicates access to the registers (read or write)
|
reg RegAccessTck; // Indicates access to the registers (read or write)
|
reg RISCAccessTck; // Indicates access to the RISC (read or write)
|
reg RISCAccessTck0; // Indicates access to the RISC (read or write)
|
|
reg RISCAccessTck1; // Indicates access to the RISC (read or write)
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|
reg RISCAccessTck2; // Indicates access to the RISC (read or write)
|
|
reg RISCAccessTck3; // Indicates access to the RISC (read or write)
|
reg [7:0] BitCounter; // Counting bits in the ShiftDR and Exit1DR stages
|
reg [7:0] BitCounter; // Counting bits in the ShiftDR and Exit1DR stages
|
reg RW; // Read/Write bit
|
reg RW; // Read/Write bit
|
reg CrcMatch; // The crc that is shifted in and the internaly calculated crc are equal
|
reg CrcMatch; // The crc that is shifted in and the internaly calculated crc are equal
|
|
|
reg RegAccess_q; // Delayed signals used for accessing the registers
|
reg RegAccess_q; // Delayed signals used for accessing the registers
|
| Line 277... |
Line 283... |
wire RiscReset_reg; // RISC is reset by setting the register bit
|
wire RiscReset_reg; // RISC is reset by setting the register bit
|
wire RiscStall_trace; // RISC is stalled by trace module
|
wire RiscStall_trace; // RISC is stalled by trace module
|
|
|
|
|
wire RegisterScanChain; // Register Scan chain selected
|
wire RegisterScanChain; // Register Scan chain selected
|
wire RiscDebugScanChain; // Risc Debug Scan chain selected
|
wire RiscDebugScanChain0; // Risc Debug Scan chain selected
|
|
wire RiscDebugScanChain1; // Risc Debug Scan chain selected
|
|
wire RiscDebugScanChain2; // Risc Debug Scan chain selected
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wire RiscDebugScanChain3; // Risc Debug Scan chain selected
|
wire WishboneScanChain; // WISHBONE Scan chain selected
|
wire WishboneScanChain; // WISHBONE Scan chain selected
|
|
|
wire RiscStall_read_access; // Stalling RISC because of the read access (SPR read)
|
wire RiscStall_read_access_0; // Stalling RISC because of the read access (SPR read)
|
wire RiscStall_write_access; // Stalling RISC because of the write access (SPR write)
|
wire RiscStall_read_access_1; // Stalling RISC because of the read access (SPR read)
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|
wire RiscStall_read_access_2; // Stalling RISC because of the read access (SPR read)
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wire RiscStall_read_access_3; // Stalling RISC because of the read access (SPR read)
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wire RiscStall_write_access_0; // Stalling RISC because of the write access (SPR write)
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wire RiscStall_write_access_1; // Stalling RISC because of the write access (SPR write)
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wire RiscStall_write_access_2; // Stalling RISC because of the write access (SPR write)
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wire RiscStall_write_access_3; // Stalling RISC because of the write access (SPR write)
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wire RiscStall_access; // Stalling RISC because of the read or write access
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wire RiscStall_access; // Stalling RISC because of the read or write access
|
|
|
wire BitCounter_Lt4;
|
wire BitCounter_Lt4;
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wire BitCounter_Eq5;
|
wire BitCounter_Eq5;
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wire BitCounter_Eq32;
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wire BitCounter_Eq32;
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| Line 387... |
Line 402... |
if(CHAIN_SELECTSelected & ShiftDR)
|
if(CHAIN_SELECTSelected & ShiftDR)
|
JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
|
JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
|
else
|
else
|
if(DEBUGSelected & ShiftDR)
|
if(DEBUGSelected & ShiftDR)
|
begin
|
begin
|
if(RiscDebugScanChain | WishboneScanChain)
|
if(RiscDebugScanChain0 | RiscDebugScanChain1 |
|
|
RiscDebugScanChain2 | RiscDebugScanChain3 | WishboneScanChain)
|
JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
|
JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
|
else
|
else
|
if(RegisterScanChain)
|
if(RegisterScanChain)
|
JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
|
JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
|
end
|
end
|
| Line 409... |
Line 425... |
begin
|
begin
|
if(trst)
|
if(trst)
|
select_crc_out <= 0;
|
select_crc_out <= 0;
|
else
|
else
|
if( RegisterScanChain & BitCounter_Eq5 |
|
if( RegisterScanChain & BitCounter_Eq5 |
|
RiscDebugScanChain & BitCounter_Eq32 |
|
RiscDebugScanChain0 & BitCounter_Eq32 |
|
|
RiscDebugScanChain1 & BitCounter_Eq32 |
|
|
RiscDebugScanChain2 & BitCounter_Eq32 |
|
|
RiscDebugScanChain3 & BitCounter_Eq32 |
|
WishboneScanChain & BitCounter_Eq32 )
|
WishboneScanChain & BitCounter_Eq32 )
|
select_crc_out <=#Tp tdi;
|
select_crc_out <=#Tp tdi;
|
else
|
else
|
if(CHAIN_SELECTSelected)
|
if(CHAIN_SELECTSelected)
|
select_crc_out <=#Tp 1;
|
select_crc_out <=#Tp 1;
|
| Line 466... |
Line 485... |
if(CHAIN_SELECTSelected)
|
if(CHAIN_SELECTSelected)
|
TDOData <= #Tp chain_sel_data[BitCounter]; // Received crc is sent back
|
TDOData <= #Tp chain_sel_data[BitCounter]; // Received crc is sent back
|
else
|
else
|
if(DEBUGSelected)
|
if(DEBUGSelected)
|
begin
|
begin
|
if(RiscDebugScanChain)
|
if(RiscDebugScanChain0 | RiscDebugScanChain1 | RiscDebugScanChain2 | RiscDebugScanChain3)
|
TDOData <= #Tp RISC_Data[BitCounter]; // Data read from RISC in the previous cycle is shifted out
|
TDOData <= #Tp RISC_Data[BitCounter]; // Data read from RISC in the previous cycle is shifted out
|
else
|
else
|
if(RegisterScanChain)
|
if(RegisterScanChain)
|
TDOData <= #Tp Register_Data[BitCounter]; // Data read from register in the previous cycle is shifted out
|
TDOData <= #Tp Register_Data[BitCounter]; // Data read from register in the previous cycle is shifted out
|
else
|
else
|
| Line 503... |
Line 522... |
$stop;
|
$stop;
|
end
|
end
|
else
|
else
|
if(ShiftDR & DEBUGSelected)
|
if(ShiftDR & DEBUGSelected)
|
begin
|
begin
|
if(RiscDebugScanChain & BitCounter > 73)
|
if((RiscDebugScanChain0 | RiscDebugScanChain1 | RiscDebugScanChain2 | RiscDebugScanChain3) & BitCounter > 73)
|
begin
|
begin
|
$display("\n%m Error: BitCounter is bigger then RISC_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
|
$display("\n%m Error: BitCounter is bigger then RISC_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
|
$stop;
|
$stop;
|
end
|
end
|
else
|
else
|
| Line 577... |
Line 596... |
begin
|
begin
|
ADDR[31:0] <=#Tp 32'h0;
|
ADDR[31:0] <=#Tp 32'h0;
|
DataOut[31:0] <=#Tp 32'h0;
|
DataOut[31:0] <=#Tp 32'h0;
|
RW <=#Tp 1'b0;
|
RW <=#Tp 1'b0;
|
RegAccessTck <=#Tp 1'b0;
|
RegAccessTck <=#Tp 1'b0;
|
RISCAccessTck <=#Tp 1'b0;
|
RISCAccessTck0 <=#Tp 1'b0;
|
|
RISCAccessTck1 <=#Tp 1'b0;
|
|
RISCAccessTck2 <=#Tp 1'b0;
|
|
RISCAccessTck3 <=#Tp 1'b0;
|
wb_AccessTck <=#Tp 1'h0;
|
wb_AccessTck <=#Tp 1'h0;
|
end
|
end
|
else
|
else
|
if(UpdateDR & DEBUGSelected & CrcMatch)
|
if(UpdateDR & DEBUGSelected & CrcMatch)
|
begin
|
begin
|
| Line 591... |
Line 613... |
RW <=#Tp JTAG_DR_IN[5]; // latch R/W bit
|
RW <=#Tp JTAG_DR_IN[5]; // latch R/W bit
|
DataOut[31:0] <=#Tp JTAG_DR_IN[37:6]; // latch data for write
|
DataOut[31:0] <=#Tp JTAG_DR_IN[37:6]; // latch data for write
|
RegAccessTck <=#Tp 1'b1;
|
RegAccessTck <=#Tp 1'b1;
|
end
|
end
|
else
|
else
|
if(RiscDebugScanChain)
|
if(WishboneScanChain & (!WBInProgress_tck))
|
|
begin
|
|
ADDR <=#Tp JTAG_DR_IN[31:0]; // Latching address for WISHBONE slave access
|
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
|
DataOut <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
|
wb_AccessTck <=#Tp 1'b1; //
|
|
end
|
|
else
|
|
if(RiscDebugScanChain0)
|
begin
|
begin
|
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for RISC register access
|
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for RISC register access
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
RISCAccessTck <=#Tp 1'b1;
|
RISCAccessTck0 <=#Tp 1'b1;
|
end
|
end
|
else
|
else
|
if(WishboneScanChain & (!WBInProgress_tck))
|
if(RiscDebugScanChain1)
|
begin
|
begin
|
ADDR <=#Tp JTAG_DR_IN[31:0]; // Latching address for WISHBONE slave access
|
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for RISC register access
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
DataOut <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
wb_AccessTck <=#Tp 1'b1; //
|
RISCAccessTck1 <=#Tp 1'b1;
|
|
end
|
|
else
|
|
if(RiscDebugScanChain2)
|
|
begin
|
|
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for RISC register access
|
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
|
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
|
RISCAccessTck2 <=#Tp 1'b1;
|
|
end
|
|
else
|
|
if(RiscDebugScanChain3)
|
|
begin
|
|
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for RISC register access
|
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
|
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
|
RISCAccessTck3 <=#Tp 1'b1;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RegAccessTck <=#Tp 1'b0; // This signals are valid for one tck clock period only
|
RegAccessTck <=#Tp 1'b0; // This signals are valid for one tck clock period only
|
RISCAccessTck <=#Tp 1'b0;
|
|
wb_AccessTck <=#Tp 1'b0;
|
wb_AccessTck <=#Tp 1'b0;
|
|
RISCAccessTck0 <=#Tp 1'b0;
|
|
RISCAccessTck1 <=#Tp 1'b0;
|
|
RISCAccessTck2 <=#Tp 1'b0;
|
|
RISCAccessTck3 <=#Tp 1'b0;
|
end
|
end
|
end
|
end
|
|
|
|
|
assign wb_adr_o = ADDR;
|
assign wb_adr_o = ADDR;
|
| Line 628... |
Line 677... |
// Synchronizing the RegAccess signal to risc_clk_i clock
|
// Synchronizing the RegAccess signal to risc_clk_i clock
|
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
.set2(RegAccessTck), .sync_out(RegAccess)
|
.set2(RegAccessTck), .sync_out(RegAccess)
|
);
|
);
|
|
|
// Synchronizing the RISCAccess signal to risc_clk_i clock
|
// Synchronizing the wb_Access signal to wishbone clock
|
dbg_sync_clk1_clk2 syn2 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
dbg_sync_clk1_clk2 syn2 (.clk1(wb_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
.set2(RISCAccessTck), .sync_out(RISCAccess)
|
.set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
|
);
|
);
|
|
|
|
// Synchronizing the RISCAccess0 signal to risc_clk_i clock
|
|
dbg_sync_clk1_clk2 syn3 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
|
.set2(RISCAccessTck0), .sync_out(RISCAccess0)
|
|
);
|
|
|
// Synchronizing the wb_Access signal to wishbone clock
|
// Synchronizing the RISCAccess1 signal to risc_clk_i clock
|
dbg_sync_clk1_clk2 syn3 (.clk1(wb_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
dbg_sync_clk1_clk2 syn4 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
.set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
|
.set2(RISCAccessTck1), .sync_out(RISCAccess1)
|
|
);
|
|
|
|
// Synchronizing the RISCAccess2 signal to risc_clk_i clock
|
|
dbg_sync_clk1_clk2 syn5 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
|
.set2(RISCAccessTck2), .sync_out(RISCAccess2)
|
|
);
|
|
|
|
// Synchronizing the RISCAccess3 signal to risc_clk_i clock
|
|
dbg_sync_clk1_clk2 syn6 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
|
.set2(RISCAccessTck3), .sync_out(RISCAccess3)
|
);
|
);
|
|
|
|
|
|
|
|
|
| Line 658... |
Line 721... |
end
|
end
|
else
|
else
|
begin
|
begin
|
RegAccess_q <=#Tp RegAccess;
|
RegAccess_q <=#Tp RegAccess;
|
RegAccess_q2 <=#Tp RegAccess_q;
|
RegAccess_q2 <=#Tp RegAccess_q;
|
RISCAccess_q <=#Tp RISCAccess;
|
RISCAccess_q <=#Tp RISCAccess0 | RISCAccess1 | RISCAccess2 | RISCAccess3;
|
RISCAccess_q2 <=#Tp RISCAccess_q;
|
RISCAccess_q2 <=#Tp RISCAccess_q;
|
RISCAccess_q3 <=#Tp RISCAccess_q2;
|
RISCAccess_q3 <=#Tp RISCAccess_q2;
|
end
|
end
|
end
|
end
|
|
|
// Chip select and read/write signals for accessing RISC
|
// Chip select and read/write signals for accessing RISC
|
assign RiscStall_write_access = RISCAccess & ~RISCAccess_q2 & RW;
|
assign RiscStall_write_access_0 = RISCAccess0 & ~RISCAccess_q2 & RW;
|
assign RiscStall_read_access = RISCAccess & ~RISCAccess_q2 & ~RW;
|
assign RiscStall_read_access_0 = RISCAccess0 & ~RISCAccess_q2 & ~RW;
|
assign RiscStall_access = RISCAccess & ~RISCAccess_q3;
|
assign RiscStall_write_access_1 = RISCAccess1 & ~RISCAccess_q2 & RW;
|
|
assign RiscStall_read_access_1 = RISCAccess1 & ~RISCAccess_q2 & ~RW;
|
|
assign RiscStall_write_access_2 = RISCAccess2 & ~RISCAccess_q2 & RW;
|
|
assign RiscStall_read_access_2 = RISCAccess2 & ~RISCAccess_q2 & ~RW;
|
|
assign RiscStall_write_access_3 = RISCAccess3 & ~RISCAccess_q2 & RW;
|
|
assign RiscStall_read_access_3 = RISCAccess3 & ~RISCAccess_q2 & ~RW;
|
|
assign RiscStall_access = (RISCAccess0 | RISCAccess1 | RISCAccess2 | RISCAccess3) & ~RISCAccess_q3;
|
|
|
|
|
reg wb_Access_wbClk_q;
|
reg wb_Access_wbClk_q;
|
// Delayed signals used for accessing WISHBONE
|
// Delayed signals used for accessing WISHBONE
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
| Line 768... |
Line 837... |
|
|
assign reset_o = RiscReset_reg;
|
assign reset_o = RiscReset_reg;
|
|
|
|
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
always @ (RiscStall_write_access or RiscStall_read_access or opselect_trace)
|
always @ (RiscStall_write_access_0 or RiscStall_write_access_1 or
|
|
RiscStall_write_access_2 or RiscStall_write_access_2 or
|
|
RiscStall_read_access_0 or RiscStall_read_access_1 or
|
|
RiscStall_read_access_2 or RiscStall_read_access_3 or opselect_trace)
|
`else
|
`else
|
always @ (RiscStall_write_access or RiscStall_read_access)
|
always @ (RiscStall_write_access_0 or RiscStall_write_access_1 or
|
|
RiscStall_write_access_2 or RiscStall_write_access_3 or
|
|
RiscStall_read_access_0 or RiscStall_read_access_1 or
|
|
RiscStall_read_access_2 or RiscStall_read_access_3)
|
`endif
|
`endif
|
begin
|
begin
|
if(RiscStall_write_access)
|
if(RiscStall_write_access_0)
|
opselect_o = `DEBUG_WRITE_SPR; // Write spr
|
opselect_o = `DEBUG_WRITE_0;
|
|
else
|
|
if(RiscStall_read_access_0)
|
|
opselect_o = `DEBUG_READ_0;
|
|
else
|
|
if(RiscStall_write_access_1)
|
|
opselect_o = `DEBUG_WRITE_1;
|
|
else
|
|
if(RiscStall_read_access_1)
|
|
opselect_o = `DEBUG_READ_1;
|
|
else
|
|
if(RiscStall_write_access_2)
|
|
opselect_o = `DEBUG_WRITE_2;
|
|
else
|
|
if(RiscStall_read_access_2)
|
|
opselect_o = `DEBUG_READ_2;
|
|
else
|
|
if(RiscStall_write_access_3)
|
|
opselect_o = `DEBUG_WRITE_3;
|
else
|
else
|
if(RiscStall_read_access)
|
if(RiscStall_read_access_3)
|
opselect_o = `DEBUG_READ_SPR; // Read spr
|
opselect_o = `DEBUG_READ_3;
|
else
|
else
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
opselect_o = opselect_trace;
|
opselect_o = opselect_trace;
|
`else
|
`else
|
opselect_o = 3'h0;
|
opselect_o = 3'h0;
|
| Line 932... |
Line 1025... |
|
|
|
|
wire EnableCrcIn = ShiftDR &
|
wire EnableCrcIn = ShiftDR &
|
( (CHAIN_SELECTSelected & BitCounter_Lt4) |
|
( (CHAIN_SELECTSelected & BitCounter_Lt4) |
|
((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
|
((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
|
((DEBUGSelected & RiscDebugScanChain) & BitCounter_Lt65)|
|
((DEBUGSelected & RiscDebugScanChain0) & BitCounter_Lt65)|
|
|
((DEBUGSelected & RiscDebugScanChain1) & BitCounter_Lt65)|
|
|
((DEBUGSelected & RiscDebugScanChain2) & BitCounter_Lt65)|
|
|
((DEBUGSelected & RiscDebugScanChain3) & BitCounter_Lt65)|
|
((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
|
((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
|
);
|
);
|
|
|
wire EnableCrcOut= ShiftDR &
|
wire EnableCrcOut= ShiftDR &
|
(
|
(
|
((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
|
((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
|
((DEBUGSelected & RiscDebugScanChain) & BitCounter_Lt65)|
|
((DEBUGSelected & RiscDebugScanChain0) & BitCounter_Lt65)|
|
|
((DEBUGSelected & RiscDebugScanChain1) & BitCounter_Lt65)|
|
|
((DEBUGSelected & RiscDebugScanChain2) & BitCounter_Lt65)|
|
|
((DEBUGSelected & RiscDebugScanChain3) & BitCounter_Lt65)|
|
((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
|
((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
|
|
|
|
((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
|
((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
|
`endif
|
`endif
|
| Line 971... |
Line 1070... |
else
|
else
|
begin
|
begin
|
if(RegisterScanChain)
|
if(RegisterScanChain)
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[45:38];
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[45:38];
|
else
|
else
|
if(RiscDebugScanChain)
|
if(RiscDebugScanChain0 | RiscDebugScanChain1 | RiscDebugScanChain2 | RiscDebugScanChain3)
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
|
else
|
else
|
if(WishboneScanChain)
|
if(WishboneScanChain)
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
|
end
|
end
|
| Line 983... |
Line 1082... |
end
|
end
|
|
|
|
|
// Active chain
|
// Active chain
|
assign RegisterScanChain = Chain == `REGISTER_SCAN_CHAIN;
|
assign RegisterScanChain = Chain == `REGISTER_SCAN_CHAIN;
|
assign RiscDebugScanChain = Chain == `RISC_DEBUG_CHAIN;
|
assign RiscDebugScanChain0 = Chain == `RISC_DEBUG_CHAIN_0;
|
|
assign RiscDebugScanChain1 = Chain == `RISC_DEBUG_CHAIN_1;
|
|
assign RiscDebugScanChain2 = Chain == `RISC_DEBUG_CHAIN_2;
|
|
assign RiscDebugScanChain3 = Chain == `RISC_DEBUG_CHAIN_3;
|
assign WishboneScanChain = Chain == `WISHBONE_SCAN_CHAIN;
|
assign WishboneScanChain = Chain == `WISHBONE_SCAN_CHAIN;
|
|
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
assign TraceTestScanChain = Chain == `TRACE_TEST_CHAIN;
|
assign TraceTestScanChain = Chain == `TRACE_TEST_CHAIN;
|
`endif
|
`endif
|
