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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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//
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// Revision 1.6 2001/10/15 09:55:47 mohor
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// Wishbone interface added, few fixes for better performance,
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// hooks for boundary scan testing added.
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//
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// Revision 1.5 2001/09/24 14:06:42 mohor
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// Revision 1.5 2001/09/24 14:06:42 mohor
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// Changes connected to the OpenRISC access (SPR read, SPR write).
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// Changes connected to the OpenRISC access (SPR read, SPR write).
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//
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//
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// Revision 1.4 2001/09/20 10:11:25 mohor
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// Revision 1.4 2001/09/20 10:11:25 mohor
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// Working version. Few bugs fixed, comments added.
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// Working version. Few bugs fixed, comments added.
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Line 83... |
module dbg_top(
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module dbg_top(
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// JTAG pins
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// JTAG pins
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tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o,
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tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o,
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// Boundary Scan signals
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// Boundary Scan signals
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CaptureDR, ShiftDR, UpdateDR, EXTESTSelected, BS_CHAIN_I,
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capture_dr_o, shift_dr_o, update_dr_o, extest_selected_o, bs_chain_i,
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// RISC signals
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// RISC signals
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risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
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risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
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bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,
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bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,
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Line 110... |
input tdi_pad_i; // JTAG test data input pad
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input tdi_pad_i; // JTAG test data input pad
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output tdo_pad_o; // JTAG test data output pad
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output tdo_pad_o; // JTAG test data output pad
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// Boundary Scan signals
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// Boundary Scan signals
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output CaptureDR;
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output capture_dr_o;
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output ShiftDR;
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output shift_dr_o;
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output UpdateDR;
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output update_dr_o;
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output EXTESTSelected;
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output extest_selected_o;
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input BS_CHAIN_I;
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input bs_chain_i;
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// RISC signals
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// RISC signals
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input risc_clk_i; // Master clock (RISC clock)
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input risc_clk_i; // Master clock (RISC clock)
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input [31:0] risc_data_i; // RISC data inputs (data that is written to the RISC registers)
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input [31:0] risc_data_i; // RISC data inputs (data that is written to the RISC registers)
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wire RiscStall_read_access; // Stalling RISC because of the read access (SPR read)
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wire RiscStall_read_access; // Stalling RISC because of the read access (SPR read)
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wire RiscStall_write_access; // Stalling RISC because of the write access (SPR write)
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wire RiscStall_write_access; // Stalling RISC because of the write access (SPR write)
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wire RiscStall_access; // Stalling RISC because of the read or write access
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wire RiscStall_access; // Stalling RISC because of the read or write access
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assign capture_dr_o = CaptureDR;
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assign shift_dr_o = ShiftDR;
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assign update_dr_o = UpdateDR;
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assign extest_selected_o = EXTESTSelected;
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wire BS_CHAIN_I = bs_chain_i;
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// This signals are used only when TRACE is used in the design
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// This signals are used only when TRACE is used in the design
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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wire [39:0] TraceChain; // Chain that comes from trace module
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wire [39:0] TraceChain; // Chain that comes from trace module
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reg ReadBuffer_Tck; // Command for incrementing the trace read pointer (synchr with TCK)
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reg ReadBuffer_Tck; // Command for incrementing the trace read pointer (synchr with TCK)
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