| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.13 2001/11/27 13:37:43 mohor
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// CRC is returned when chain selection data is transmitted.
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//
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// Revision 1.12 2001/11/26 10:47:09 mohor
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// Revision 1.12 2001/11/26 10:47:09 mohor
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// Crc generation is different for read or write commands. Small synthesys fixes.
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// Crc generation is different for read or write commands. Small synthesys fixes.
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//
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//
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// Revision 1.11 2001/11/14 10:10:41 mohor
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// Revision 1.11 2001/11/14 10:10:41 mohor
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// Wishbone data latched on wb_clk_i instead of risc_clk.
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// Wishbone data latched on wb_clk_i instead of risc_clk.
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| Line 634... |
Line 637... |
else
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else
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if(ShiftDR)
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if(ShiftDR)
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JTAG_DR_IN[BitCounter]<=#Tp TDI;
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JTAG_DR_IN[BitCounter]<=#Tp TDI;
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end
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end
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wire [72:0] RISC_Data;
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wire [73:0] RISC_Data;
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wire [45:0] Register_Data;
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wire [46:0] Register_Data;
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wire [72:0] WISHBONE_Data;
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wire [73:0] WISHBONE_Data;
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wire [12:0] chain_sel_data;
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wire [12:0] chain_sel_data;
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wire wb_Access_wbClk;
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wire wb_Access_wbClk;
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// assign RISC_Data = {CalculatedCrcOut, RISC_DATAINLatch, 33'h0};
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// assign RISC_Data = {CalculatedCrcOut, RISC_DATAINLatch, 33'h0};
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// assign Register_Data = {CalculatedCrcOut, RegisterReadLatch, 6'h0};
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// assign Register_Data = {CalculatedCrcOut, RegisterReadLatch, 6'h0};
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