OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_1/] [rtl/] [verilog/] [dbg_top.v] - Diff between revs 25 and 28

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 25 Rev 28
Line 43... Line 43...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.15  2001/12/05 13:28:21  mohor
 
// trst signal is synchronized to wb_clk_i.
 
//
// Revision 1.14  2001/11/28 09:36:15  mohor
// Revision 1.14  2001/11/28 09:36:15  mohor
// Register length fixed.
// Register length fixed.
//
//
// Revision 1.13  2001/11/27 13:37:43  mohor
// Revision 1.13  2001/11/27 13:37:43  mohor
// CRC is returned when chain selection data is transmitted.
// CRC is returned when chain selection data is transmitted.
Line 107... Line 110...
`include "dbg_defines.v"
`include "dbg_defines.v"
 
 
// Top module
// Top module
module dbg_top(
module dbg_top(
                // JTAG pins
                // JTAG pins
                tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o,
                tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoen_o,
 
 
                // Boundary Scan signals
                // Boundary Scan signals
                capture_dr_o, shift_dr_o, update_dr_o, extest_selected_o, bs_chain_i, bs_chain_o,
                capture_dr_o, shift_dr_o, update_dr_o, extest_selected_o, bs_chain_i, bs_chain_o,
 
 
                // RISC signals
                // RISC signals
Line 134... Line 137...
input         tms_pad_i;                  // JTAG test mode select pad
input         tms_pad_i;                  // JTAG test mode select pad
input         tck_pad_i;                  // JTAG test clock pad
input         tck_pad_i;                  // JTAG test clock pad
input         trst_pad_i;                 // JTAG test reset pad
input         trst_pad_i;                 // JTAG test reset pad
input         tdi_pad_i;                  // JTAG test data input pad
input         tdi_pad_i;                  // JTAG test data input pad
output        tdo_pad_o;                  // JTAG test data output pad
output        tdo_pad_o;                  // JTAG test data output pad
 
output        tdo_padoen_o;               // Output enable for JTAG test data output pad 
 
 
 
 
// Boundary Scan signals
// Boundary Scan signals
output capture_dr_o;
output capture_dr_o;
output shift_dr_o;
output shift_dr_o;
Line 1132... Line 1136...
      end
      end
  endcase
  endcase
end
end
 
 
// Tristate control for tdo_pad_o pin
// Tristate control for tdo_pad_o pin
assign tdo_pad_o = (ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR)? TDOMuxed : 1'bz;
//assign tdo_pad_o = (ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR)? TDOMuxed : 1'bz;
 
assign tdo_pad_o = TDOMuxed;
 
assign tdo_padoen_o = ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR;
 
 
/**********************************************************************************
/**********************************************************************************
*                                                                                 *
*                                                                                 *
*   End: Activating Instructions                                                  *
*   End: Activating Instructions                                                  *
*                                                                                 *
*                                                                                 *

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.