URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_12/] [rtl/] [verilog/] [dbg_defines.v] - Diff between revs 63 and 65

Rev 63	Rev 65
Line 43...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.11 2003/08/28 13:55:21 simons`
	`// Three more chains added for cpu debug access.`
	`//`
`// Revision 1.10 2003/07/31 12:19:49 simons`	`// Revision 1.10 2003/07/31 12:19:49 simons`
`// Multiple cpu support added.`	`// Multiple cpu support added.`
`//`	`//`
`// Revision 1.9 2002/05/07 14:43:59 mohor`	`// Revision 1.9 2002/05/07 14:43:59 mohor`
`// mon_cntl_o signals that controls monitor mux added.`	`// mon_cntl_o signals that controls monitor mux added.`
Line 174...	Line 177...
`define SSEL_ADR 5'h03	`define SSEL_ADR 5'h03
`define RISCOP_ADR 5'h04	`define RISCOP_ADR 5'h04
`define RISCSEL_ADR 5'h05	`define RISCSEL_ADR 5'h05
`define RECSEL_ADR 5'h10	`define RECSEL_ADR 5'h10
`define MON_CNTL_ADR 5'h11	`define MON_CNTL_ADR 5'h11
	`define WB_CNTL_ADR 5'h12


`// Registers default values (after reset)`	`// Registers default values (after reset)`
`define MODER_DEF 2'h0	`define MODER_DEF 2'h0
`define TSEL_DEF 32'h00000000	`define TSEL_DEF 32'h00000000