| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.32 2003/09/18 14:00:47 simons
|
|
// Lower two address lines must be always zero.
|
|
//
|
// Revision 1.31 2003/09/17 14:38:57 simons
|
// Revision 1.31 2003/09/17 14:38:57 simons
|
// WB_CNTL register added, some syncronization fixes.
|
// WB_CNTL register added, some syncronization fixes.
|
//
|
//
|
// Revision 1.30 2003/08/28 13:55:22 simons
|
// Revision 1.30 2003/08/28 13:55:22 simons
|
// Three more chains added for cpu debug access.
|
// Three more chains added for cpu debug access.
|
| Line 56... |
Line 59... |
//
|
//
|
// Revision 1.28 2002/11/06 14:22:41 mohor
|
// Revision 1.28 2002/11/06 14:22:41 mohor
|
// Trst signal is not inverted here any more. Inverted on higher layer !!!.
|
// Trst signal is not inverted here any more. Inverted on higher layer !!!.
|
//
|
//
|
// Revision 1.27 2002/10/10 02:42:55 mohor
|
// Revision 1.27 2002/10/10 02:42:55 mohor
|
// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.
|
// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added).
|
|
// Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value,
|
|
// wb_cyc_o is negated.
|
//
|
//
|
// Revision 1.26 2002/05/07 14:43:59 mohor
|
// Revision 1.26 2002/05/07 14:43:59 mohor
|
// mon_cntl_o signals that controls monitor mux added.
|
// mon_cntl_o signals that controls monitor mux added.
|
//
|
//
|
// Revision 1.25 2002/04/22 12:54:11 mohor
|
// Revision 1.25 2002/04/22 12:54:11 mohor
|
| Line 161... |
Line 166... |
`include "dbg_defines.v"
|
`include "dbg_defines.v"
|
|
|
// Top module
|
// Top module
|
module dbg_top(
|
module dbg_top(
|
|
|
// RISC signals
|
// CPU signals
|
risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
|
cpu_clk_i, cpu_addr_o, cpu_data_i, cpu_data_o, wp_i,
|
bp_i, opselect_o, lsstatus_i, istatus_i,
|
bp_i, opselect_o, lsstatus_i, istatus_i,
|
risc_stall_o, risc_stall_all_o, risc_sel_o, reset_o,
|
cpu_stall_o, cpu_stall_all_o, cpu_sel_o, reset_o,
|
|
|
// WISHBONE common signals
|
// WISHBONE common signals
|
wb_rst_i, wb_clk_i,
|
wb_rst_i, wb_clk_i,
|
|
|
// WISHBONE master interface
|
// WISHBONE master interface
|
wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
|
wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
|
wb_we_o, wb_ack_i, wb_cab_o, wb_err_i,
|
wb_we_o, wb_ack_i, wb_cab_o, wb_err_i,
|
|
|
// TAP states
|
// TAP states
|
ShiftDR, Exit1DR, UpdateDR, UpdateDR_q,
|
ShiftDR, Exit1DR, UpdateDR, UpdateDR_q, SelectDRScan,
|
|
|
// Instructions
|
// Instructions
|
IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected,
|
IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected,
|
|
|
// TAP signals
|
// TAP signals
|
trst_in, tck, tdi, TDOData,
|
trst_in, tck, tdi, TDOData,
|
|
|
BypassRegister,
|
BypassRegister,
|
|
|
// Monitor mux control
|
// Monitor mux control
|
mon_cntl_o
|
mon_cntl_o,
|
|
|
|
// Selected chains
|
|
RegisterScanChain,
|
|
CpuDebugScanChain0,
|
|
CpuDebugScanChain1,
|
|
CpuDebugScanChain2,
|
|
CpuDebugScanChain3,
|
|
WishboneScanChain
|
|
|
|
|
|
|
);
|
);
|
|
|
parameter Tp = 1;
|
parameter Tp = 1;
|
|
|
|
|
// RISC signals
|
// CPU signals
|
input risc_clk_i; // Master clock (RISC clock)
|
input cpu_clk_i; // Master clock (CPU clock)
|
input [31:0] risc_data_i; // RISC data inputs (data that is written to the RISC registers)
|
input [31:0] cpu_data_i; // CPU data inputs (data that is written to the CPU registers)
|
input [10:0] wp_i; // Watchpoint inputs
|
input [10:0] wp_i; // Watchpoint inputs
|
input bp_i; // Breakpoint input
|
input bp_i; // Breakpoint input
|
input [3:0] lsstatus_i; // Load/store status inputs
|
input [3:0] lsstatus_i; // Load/store status inputs
|
input [1:0] istatus_i; // Instruction status inputs
|
input [1:0] istatus_i; // Instruction status inputs
|
output [31:0] risc_addr_o; // RISC address output (for adressing registers within RISC)
|
output [31:0] cpu_addr_o; // CPU address output (for adressing registers within CPU)
|
output [31:0] risc_data_o; // RISC data output (data read from risc registers)
|
output [31:0] cpu_data_o; // CPU data output (data read from cpu registers)
|
output [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
|
output [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the cpu_data_i)
|
output risc_stall_o; // Stalls the selected RISC
|
output cpu_stall_o; // Stalls the selected CPU
|
output risc_stall_all_o; // Stalls all the rest RISCs
|
output cpu_stall_all_o; // Stalls all the rest CPUs
|
output [`RISC_NUM-1:0] risc_sel_o; // Stalls all the rest RISCs
|
output [`CPU_NUM-1:0] cpu_sel_o; // Stalls all the rest CPUs
|
output reset_o; // Resets the RISC
|
output reset_o; // Resets the CPU
|
|
|
|
|
// WISHBONE common signals
|
// WISHBONE common signals
|
input wb_rst_i; // WISHBONE reset
|
input wb_rst_i; // WISHBONE reset
|
input wb_clk_i; // WISHBONE clock
|
input wb_clk_i; // WISHBONE clock
|
| Line 229... |
Line 244... |
// TAP states
|
// TAP states
|
input ShiftDR;
|
input ShiftDR;
|
input Exit1DR;
|
input Exit1DR;
|
input UpdateDR;
|
input UpdateDR;
|
input UpdateDR_q;
|
input UpdateDR_q;
|
|
input SelectDRScan;
|
|
|
input trst_in;
|
input trst_in;
|
input tck;
|
input tck;
|
input tdi;
|
input tdi;
|
|
|
| Line 244... |
Line 260... |
// Defining which instruction is selected
|
// Defining which instruction is selected
|
input IDCODESelected;
|
input IDCODESelected;
|
input CHAIN_SELECTSelected;
|
input CHAIN_SELECTSelected;
|
input DEBUGSelected;
|
input DEBUGSelected;
|
|
|
|
// Selected chains
|
|
output RegisterScanChain;
|
|
output CpuDebugScanChain0;
|
|
output CpuDebugScanChain1;
|
|
output CpuDebugScanChain2;
|
|
output CpuDebugScanChain3;
|
|
output WishboneScanChain;
|
|
|
reg wb_cyc_o;
|
reg wb_cyc_o;
|
|
|
reg [31:0] ADDR;
|
reg [31:0] ADDR;
|
reg [31:0] DataOut;
|
reg [31:0] DataOut;
|
|
|
reg [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
|
reg [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the cpu_data_i)
|
|
|
reg [`CHAIN_ID_LENGTH-1:0] Chain; // Selected chain
|
reg [`CHAIN_ID_LENGTH-1:0] Chain; // Selected chain
|
reg [31:0] DataReadLatch; // Data when reading register or RISC is latched one risc_clk_i clock after the data is read.
|
reg [31:0] DataReadLatch; // Data when reading register or CPU is latched one cpu_clk_i clock after the data is read.
|
reg RegAccessTck; // Indicates access to the registers (read or write)
|
reg RegAccessTck; // Indicates access to the registers (read or write)
|
reg RISCAccessTck0; // Indicates access to the RISC (read or write)
|
reg CPUAccessTck0; // Indicates access to the CPU (read or write)
|
reg RISCAccessTck1; // Indicates access to the RISC (read or write)
|
reg CPUAccessTck1; // Indicates access to the CPU (read or write)
|
reg RISCAccessTck2; // Indicates access to the RISC (read or write)
|
reg CPUAccessTck2; // Indicates access to the CPU (read or write)
|
reg RISCAccessTck3; // Indicates access to the RISC (read or write)
|
reg CPUAccessTck3; // Indicates access to the CPU (read or write)
|
reg [7:0] BitCounter; // Counting bits in the ShiftDR and Exit1DR stages
|
reg [7:0] BitCounter; // Counting bits in the ShiftDR and Exit1DR stages
|
reg RW; // Read/Write bit
|
reg RW; // Read/Write bit
|
reg CrcMatch; // The crc that is shifted in and the internaly calculated crc are equal
|
reg CrcMatch; // The crc that is shifted in and the internaly calculated crc are equal
|
|
reg CrcMatch_q;
|
|
|
reg RegAccess_q; // Delayed signals used for accessing the registers
|
reg RegAccess_q; // Delayed signals used for accessing the registers
|
reg RegAccess_q2; // Delayed signals used for accessing the registers
|
reg RegAccess_q2; // Delayed signals used for accessing the registers
|
reg RISCAccess_q; // Delayed signals used for accessing the RISC
|
reg CPUAccess_q; // Delayed signals used for accessing the CPU
|
reg RISCAccess_q2; // Delayed signals used for accessing the RISC
|
reg CPUAccess_q2; // Delayed signals used for accessing the CPU
|
reg RISCAccess_q3; // Delayed signals used for accessing the RISC
|
reg CPUAccess_q3; // Delayed signals used for accessing the CPU
|
|
|
reg wb_AccessTck; // Indicates access to the WISHBONE
|
reg wb_AccessTck; // Indicates access to the WISHBONE
|
reg [31:0] WBReadLatch; // Data latched during WISHBONE read
|
reg [31:0] WBReadLatch; // Data latched during WISHBONE read
|
reg WBErrorLatch; // Error latched during WISHBONE read
|
reg WBErrorLatch; // Error latched during WISHBONE read
|
reg WBInProgress; // WISHBONE access is in progress
|
reg WBInProgress; // WISHBONE access is in progress
|
| Line 283... |
Line 308... |
|
|
|
|
wire [31:0] RegDataIn; // Data from registers (read data)
|
wire [31:0] RegDataIn; // Data from registers (read data)
|
wire [`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
|
wire [`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
|
|
|
wire RiscStall_reg; // RISC is stalled by setting the register bit
|
wire CpuStall_reg; // CPU is stalled by setting the register bit
|
wire RiscReset_reg; // RISC is reset by setting the register bit
|
wire CpuReset_reg; // CPU is reset by setting the register bit
|
wire RiscStall_trace; // RISC is stalled by trace module
|
wire CpuStall_trace; // CPU is stalled by trace module
|
|
|
|
|
wire RegisterScanChain; // Register Scan chain selected
|
wire CpuStall_read_access_0; // Stalling Cpu because of the read access (SPR read)
|
wire RiscDebugScanChain0; // Risc Debug Scan chain selected
|
wire CpuStall_read_access_1; // Stalling Cpu because of the read access (SPR read)
|
wire RiscDebugScanChain1; // Risc Debug Scan chain selected
|
wire CpuStall_read_access_2; // Stalling Cpu because of the read access (SPR read)
|
wire RiscDebugScanChain2; // Risc Debug Scan chain selected
|
wire CpuStall_read_access_3; // Stalling Cpu because of the read access (SPR read)
|
wire RiscDebugScanChain3; // Risc Debug Scan chain selected
|
wire CpuStall_write_access_0; // Stalling Cpu because of the write access (SPR write)
|
wire WishboneScanChain; // WISHBONE Scan chain selected
|
wire CpuStall_write_access_1; // Stalling Cpu because of the write access (SPR write)
|
|
wire CpuStall_write_access_2; // Stalling Cpu because of the write access (SPR write)
|
wire RiscStall_read_access_0; // Stalling RISC because of the read access (SPR read)
|
wire CpuStall_write_access_3; // Stalling Cpu because of the write access (SPR write)
|
wire RiscStall_read_access_1; // Stalling RISC because of the read access (SPR read)
|
wire CpuStall_access; // Stalling Cpu because of the read or write access
|
wire RiscStall_read_access_2; // Stalling RISC because of the read access (SPR read)
|
|
wire RiscStall_read_access_3; // Stalling RISC because of the read access (SPR read)
|
|
wire RiscStall_write_access_0; // Stalling RISC because of the write access (SPR write)
|
|
wire RiscStall_write_access_1; // Stalling RISC because of the write access (SPR write)
|
|
wire RiscStall_write_access_2; // Stalling RISC because of the write access (SPR write)
|
|
wire RiscStall_write_access_3; // Stalling RISC because of the write access (SPR write)
|
|
wire RiscStall_access; // Stalling RISC because of the read or write access
|
|
|
|
wire BitCounter_Lt4;
|
wire BitCounter_Lt4;
|
wire BitCounter_Eq5;
|
wire BitCounter_Eq5;
|
wire BitCounter_Eq32;
|
wire BitCounter_Eq32;
|
wire BitCounter_Lt38;
|
wire BitCounter_Lt38;
|
| Line 372... |
Line 390... |
|
|
wire TraceTestScanChain; // Trace Test Scan chain selected
|
wire TraceTestScanChain; // Trace Test Scan chain selected
|
wire [47:0] Trace_Data; // Trace data
|
wire [47:0] Trace_Data; // Trace data
|
|
|
wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of
|
wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of
|
// data is set to the risc_data_i)
|
// data is set to the cpu_data_i)
|
wire BitCounter_Lt40;
|
wire BitCounter_Lt40;
|
|
|
`endif
|
`endif
|
|
|
|
|
| Line 408... |
Line 426... |
if(CHAIN_SELECTSelected & ShiftDR)
|
if(CHAIN_SELECTSelected & ShiftDR)
|
JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
|
JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
|
else
|
else
|
if(DEBUGSelected & ShiftDR)
|
if(DEBUGSelected & ShiftDR)
|
begin
|
begin
|
if(RiscDebugScanChain0 | RiscDebugScanChain1 |
|
if(CpuDebugScanChain0 | CpuDebugScanChain1 |
|
RiscDebugScanChain2 | RiscDebugScanChain3 | WishboneScanChain)
|
CpuDebugScanChain2 | CpuDebugScanChain3 | WishboneScanChain)
|
JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
|
JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
|
else
|
else
|
if(RegisterScanChain)
|
if(RegisterScanChain)
|
JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
|
JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
|
end
|
end
|
end
|
end
|
|
|
wire [73:0] RISC_Data;
|
wire [73:0] CPU_Data;
|
wire [46:0] Register_Data;
|
wire [46:0] Register_Data;
|
wire [73:0] WISHBONE_Data;
|
wire [73:0] WISHBONE_Data;
|
wire [12:0] chain_sel_data;
|
wire [12:0] chain_sel_data;
|
wire wb_Access_wbClk;
|
wire wb_Access_wbClk;
|
wire [1:0] wb_cntl_o;
|
wire [1:0] wb_cntl_o;
|
|
|
|
|
reg select_crc_out;
|
reg crc_bypassed;
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
select_crc_out <= 0;
|
crc_bypassed <= 0;
|
else
|
else if (CHAIN_SELECTSelected)
|
if( RegisterScanChain & BitCounter_Eq5 |
|
crc_bypassed <=#Tp 1;
|
RiscDebugScanChain0 & BitCounter_Eq32 |
|
else if(
|
RiscDebugScanChain1 & BitCounter_Eq32 |
|
RegisterScanChain & BitCounter_Eq5 |
|
RiscDebugScanChain2 & BitCounter_Eq32 |
|
CpuDebugScanChain0 & BitCounter_Eq32 |
|
RiscDebugScanChain3 & BitCounter_Eq32 |
|
CpuDebugScanChain1 & BitCounter_Eq32 |
|
|
CpuDebugScanChain2 & BitCounter_Eq32 |
|
|
CpuDebugScanChain3 & BitCounter_Eq32 |
|
WishboneScanChain & BitCounter_Eq32 )
|
WishboneScanChain & BitCounter_Eq32 )
|
select_crc_out <=#Tp tdi;
|
crc_bypassed <=#Tp tdi; // when write is performed.
|
else
|
|
if(CHAIN_SELECTSelected)
|
|
select_crc_out <=#Tp 1;
|
|
else
|
|
if(UpdateDR)
|
|
select_crc_out <=#Tp 0;
|
|
end
|
end
|
|
|
wire [8:0] send_crc;
|
reg [7:0] send_crc;
|
|
wire [7:0] CalculatedCrcIn; // crc calculated from the input data (shifted in)
|
|
|
assign send_crc = select_crc_out? {9{BypassRegister}} : // Calculated CRC is returned when read operation is
|
// Calculated CRC is returned when read operation is performed, else received crc is returned (loopback).
|
{CalculatedCrcOut, 1'b0} ; // performed, else received crc is returned (loopback).
|
always @ (crc_bypassed or CrcMatch or CrcMatch_q or BypassRegister or CalculatedCrcOut)
|
|
begin
|
|
if (crc_bypassed)
|
|
begin
|
|
if (CrcMatch | CrcMatch_q) // When crc is looped back, first bit is not inverted
|
|
send_crc = {8{BypassRegister}}; // since it caused the error. By inverting it we would
|
|
else // get ok crc.
|
|
send_crc = {8{~BypassRegister}};
|
|
end
|
|
else
|
|
begin
|
|
if (CrcMatch)
|
|
send_crc = {8{CalculatedCrcOut}};
|
|
else
|
|
send_crc = {8{~CalculatedCrcOut}};
|
|
end
|
|
end
|
|
|
assign RISC_Data = {send_crc, DataReadLatch, 33'h0};
|
assign CPU_Data = {send_crc, DataReadLatch, 33'h0, 1'b0};
|
assign Register_Data = {send_crc, DataReadLatch, 6'h0};
|
assign Register_Data = {send_crc, DataReadLatch, 6'h0, 1'b0};
|
assign WISHBONE_Data = {send_crc, WBReadLatch, 31'h0, WBInProgress, WBErrorLatch};
|
assign WISHBONE_Data = {send_crc, WBReadLatch, 31'h0, WBInProgress, WBErrorLatch, 1'b0};
|
assign chain_sel_data = {send_crc, 4'h0};
|
assign chain_sel_data = {send_crc, 4'h0, 1'b0};
|
|
|
|
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
assign Trace_Data = {CalculatedCrcOut, TraceChain};
|
assign Trace_Data = {CalculatedCrcOut, TraceChain};
|
`endif
|
`endif
|
| Line 492... |
Line 523... |
if(CHAIN_SELECTSelected)
|
if(CHAIN_SELECTSelected)
|
TDOData <= #Tp chain_sel_data[BitCounter]; // Received crc is sent back
|
TDOData <= #Tp chain_sel_data[BitCounter]; // Received crc is sent back
|
else
|
else
|
if(DEBUGSelected)
|
if(DEBUGSelected)
|
begin
|
begin
|
if(RiscDebugScanChain0 | RiscDebugScanChain1 | RiscDebugScanChain2 | RiscDebugScanChain3)
|
if(CpuDebugScanChain0 | CpuDebugScanChain1 | CpuDebugScanChain2 | CpuDebugScanChain3)
|
TDOData <= #Tp RISC_Data[BitCounter]; // Data read from RISC in the previous cycle is shifted out
|
TDOData <= #Tp CPU_Data[BitCounter]; // Data read from CPU in the previous cycle is shifted out
|
else
|
else
|
if(RegisterScanChain)
|
if(RegisterScanChain)
|
TDOData <= #Tp Register_Data[BitCounter]; // Data read from register in the previous cycle is shifted out
|
TDOData <= #Tp Register_Data[BitCounter]; // Data read from register in the previous cycle is shifted out
|
else
|
else
|
if(WishboneScanChain)
|
if(WishboneScanChain)
|
| Line 529... |
Line 560... |
$stop;
|
$stop;
|
end
|
end
|
else
|
else
|
if(ShiftDR & DEBUGSelected)
|
if(ShiftDR & DEBUGSelected)
|
begin
|
begin
|
if((RiscDebugScanChain0 | RiscDebugScanChain1 | RiscDebugScanChain2 | RiscDebugScanChain3) & BitCounter > 73)
|
if((CpuDebugScanChain0 | CpuDebugScanChain1 | CpuDebugScanChain2 | CpuDebugScanChain3) & BitCounter > 73)
|
begin
|
begin
|
$display("\n%m Error: BitCounter is bigger then RISC_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
|
$display("\n%m Error: BitCounter is bigger then CPU_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
|
$stop;
|
$stop;
|
end
|
end
|
else
|
else
|
if(RegisterScanChain & BitCounter > 46)
|
if(RegisterScanChain & BitCounter > 46)
|
begin
|
begin
|
$display("\n%m Error: BitCounter is bigger then RISC_Data bits width[46:0]. BitCounter=%d\n",BitCounter);
|
$display("\n%m Error: BitCounter is bigger then Register_Data bits width[46:0]. BitCounter=%d\n",BitCounter);
|
$stop;
|
$stop;
|
end
|
end
|
else
|
else
|
if(WishboneScanChain & BitCounter > 73)
|
if(WishboneScanChain & BitCounter > 73)
|
begin
|
begin
|
| Line 592... |
Line 623... |
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* Register read/write logic *
|
* Register read/write logic *
|
* RISC registers read/write logic *
|
* CPU registers read/write logic *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
begin
|
begin
|
ADDR[31:0] <=#Tp 32'h0;
|
ADDR[31:0] <=#Tp 32'h0;
|
DataOut[31:0] <=#Tp 32'h0;
|
DataOut[31:0] <=#Tp 32'h0;
|
RW <=#Tp 1'b0;
|
RW <=#Tp 1'b0;
|
RegAccessTck <=#Tp 1'b0;
|
RegAccessTck <=#Tp 1'b0;
|
RISCAccessTck0 <=#Tp 1'b0;
|
CPUAccessTck0 <=#Tp 1'b0;
|
RISCAccessTck1 <=#Tp 1'b0;
|
CPUAccessTck1 <=#Tp 1'b0;
|
RISCAccessTck2 <=#Tp 1'b0;
|
CPUAccessTck2 <=#Tp 1'b0;
|
RISCAccessTck3 <=#Tp 1'b0;
|
CPUAccessTck3 <=#Tp 1'b0;
|
wb_AccessTck <=#Tp 1'h0;
|
wb_AccessTck <=#Tp 1'h0;
|
end
|
end
|
else
|
else
|
if(UpdateDR & DEBUGSelected & CrcMatch)
|
if(UpdateDR & DEBUGSelected & CrcMatch)
|
begin
|
begin
|
| Line 628... |
Line 659... |
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
DataOut <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
DataOut <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
wb_AccessTck <=#Tp 1'b1; //
|
wb_AccessTck <=#Tp 1'b1; //
|
end
|
end
|
else
|
else
|
if(RiscDebugScanChain0)
|
if(CpuDebugScanChain0)
|
begin
|
begin
|
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for RISC register access
|
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for CPU register access
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
RISCAccessTck0 <=#Tp 1'b1;
|
CPUAccessTck0 <=#Tp 1'b1;
|
end
|
end
|
else
|
else
|
if(RiscDebugScanChain1)
|
if(CpuDebugScanChain1)
|
begin
|
begin
|
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for RISC register access
|
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for CPU register access
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
RISCAccessTck1 <=#Tp 1'b1;
|
CPUAccessTck1 <=#Tp 1'b1;
|
end
|
end
|
else
|
else
|
if(RiscDebugScanChain2)
|
if(CpuDebugScanChain2)
|
begin
|
begin
|
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for RISC register access
|
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for CPU register access
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
RISCAccessTck2 <=#Tp 1'b1;
|
CPUAccessTck2 <=#Tp 1'b1;
|
end
|
end
|
else
|
else
|
if(RiscDebugScanChain3)
|
if(CpuDebugScanChain3)
|
begin
|
begin
|
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for RISC register access
|
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for CPU register access
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
RISCAccessTck3 <=#Tp 1'b1;
|
CPUAccessTck3 <=#Tp 1'b1;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RegAccessTck <=#Tp 1'b0; // This signals are valid for one tck clock period only
|
RegAccessTck <=#Tp 1'b0; // This signals are valid for one tck clock period only
|
wb_AccessTck <=#Tp 1'b0;
|
wb_AccessTck <=#Tp 1'b0;
|
RISCAccessTck0 <=#Tp 1'b0;
|
CPUAccessTck0 <=#Tp 1'b0;
|
RISCAccessTck1 <=#Tp 1'b0;
|
CPUAccessTck1 <=#Tp 1'b0;
|
RISCAccessTck2 <=#Tp 1'b0;
|
CPUAccessTck2 <=#Tp 1'b0;
|
RISCAccessTck3 <=#Tp 1'b0;
|
CPUAccessTck3 <=#Tp 1'b0;
|
end
|
end
|
end
|
end
|
|
|
|
|
assign wb_adr_o = {ADDR[31:2] & {30{wb_cyc_o}}, 2'b0};
|
assign wb_adr_o = {ADDR[31:2] & {30{wb_cyc_o}}, 2'b0};
|
| Line 707... |
Line 738... |
endcase
|
endcase
|
else
|
else
|
wb_sel_o = 4'hx;
|
wb_sel_o = 4'hx;
|
end
|
end
|
|
|
// Synchronizing the RegAccess signal to risc_clk_i clock
|
// Synchronizing the RegAccess signal to cpu_clk_i clock
|
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
dbg_sync_clk1_clk2 syn1 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
.set2(RegAccessTck), .sync_out(RegAccess)
|
.set2(RegAccessTck), .sync_out(RegAccess)
|
);
|
);
|
|
|
// Synchronizing the wb_Access signal to wishbone clock
|
// Synchronizing the wb_Access signal to wishbone clock
|
dbg_sync_clk1_clk2 syn2 (.clk1(wb_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
dbg_sync_clk1_clk2 syn2 (.clk1(wb_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
.set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
|
.set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
|
);
|
);
|
|
|
// Synchronizing the RISCAccess0 signal to risc_clk_i clock
|
// Synchronizing the CPUAccess0 signal to cpu_clk_i clock
|
dbg_sync_clk1_clk2 syn3 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
dbg_sync_clk1_clk2 syn3 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
.set2(RISCAccessTck0), .sync_out(RISCAccess0)
|
.set2(CPUAccessTck0), .sync_out(CPUAccess0)
|
);
|
);
|
|
|
// Synchronizing the RISCAccess1 signal to risc_clk_i clock
|
// Synchronizing the CPUAccess1 signal to cpu_clk_i clock
|
dbg_sync_clk1_clk2 syn4 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
dbg_sync_clk1_clk2 syn4 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
.set2(RISCAccessTck1), .sync_out(RISCAccess1)
|
.set2(CPUAccessTck1), .sync_out(CPUAccess1)
|
);
|
);
|
|
|
// Synchronizing the RISCAccess2 signal to risc_clk_i clock
|
// Synchronizing the CPUAccess2 signal to cpu_clk_i clock
|
dbg_sync_clk1_clk2 syn5 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
dbg_sync_clk1_clk2 syn5 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
.set2(RISCAccessTck2), .sync_out(RISCAccess2)
|
.set2(CPUAccessTck2), .sync_out(CPUAccess2)
|
);
|
);
|
|
|
// Synchronizing the RISCAccess3 signal to risc_clk_i clock
|
// Synchronizing the CPUAccess3 signal to cpu_clk_i clock
|
dbg_sync_clk1_clk2 syn6 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
dbg_sync_clk1_clk2 syn6 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
.set2(RISCAccessTck3), .sync_out(RISCAccess3)
|
.set2(CPUAccessTck3), .sync_out(CPUAccess3)
|
);
|
);
|
|
|
|
|
|
|
|
|
|
|
// Delayed signals used for accessing registers and RISC
|
// Delayed signals used for accessing registers and CPU
|
always @ (posedge risc_clk_i or posedge wb_rst_i)
|
always @ (posedge cpu_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
begin
|
begin
|
RegAccess_q <=#Tp 1'b0;
|
RegAccess_q <=#Tp 1'b0;
|
RegAccess_q2 <=#Tp 1'b0;
|
RegAccess_q2 <=#Tp 1'b0;
|
RISCAccess_q <=#Tp 1'b0;
|
CPUAccess_q <=#Tp 1'b0;
|
RISCAccess_q2 <=#Tp 1'b0;
|
CPUAccess_q2 <=#Tp 1'b0;
|
RISCAccess_q3 <=#Tp 1'b0;
|
CPUAccess_q3 <=#Tp 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RegAccess_q <=#Tp RegAccess;
|
RegAccess_q <=#Tp RegAccess;
|
RegAccess_q2 <=#Tp RegAccess_q;
|
RegAccess_q2 <=#Tp RegAccess_q;
|
RISCAccess_q <=#Tp RISCAccess0 | RISCAccess1 | RISCAccess2 | RISCAccess3;
|
CPUAccess_q <=#Tp CPUAccess0 | CPUAccess1 | CPUAccess2 | CPUAccess3;
|
RISCAccess_q2 <=#Tp RISCAccess_q;
|
CPUAccess_q2 <=#Tp CPUAccess_q;
|
RISCAccess_q3 <=#Tp RISCAccess_q2;
|
CPUAccess_q3 <=#Tp CPUAccess_q2;
|
end
|
end
|
end
|
end
|
|
|
// Chip select and read/write signals for accessing RISC
|
// Chip select and read/write signals for accessing CPU
|
assign RiscStall_write_access_0 = RISCAccess0 & ~RISCAccess_q2 & RW;
|
assign CpuStall_write_access_0 = CPUAccess0 & ~CPUAccess_q2 & RW;
|
assign RiscStall_read_access_0 = RISCAccess0 & ~RISCAccess_q2 & ~RW;
|
assign CpuStall_read_access_0 = CPUAccess0 & ~CPUAccess_q2 & ~RW;
|
assign RiscStall_write_access_1 = RISCAccess1 & ~RISCAccess_q2 & RW;
|
assign CpuStall_write_access_1 = CPUAccess1 & ~CPUAccess_q2 & RW;
|
assign RiscStall_read_access_1 = RISCAccess1 & ~RISCAccess_q2 & ~RW;
|
assign CpuStall_read_access_1 = CPUAccess1 & ~CPUAccess_q2 & ~RW;
|
assign RiscStall_write_access_2 = RISCAccess2 & ~RISCAccess_q2 & RW;
|
assign CpuStall_write_access_2 = CPUAccess2 & ~CPUAccess_q2 & RW;
|
assign RiscStall_read_access_2 = RISCAccess2 & ~RISCAccess_q2 & ~RW;
|
assign CpuStall_read_access_2 = CPUAccess2 & ~CPUAccess_q2 & ~RW;
|
assign RiscStall_write_access_3 = RISCAccess3 & ~RISCAccess_q2 & RW;
|
assign CpuStall_write_access_3 = CPUAccess3 & ~CPUAccess_q2 & RW;
|
assign RiscStall_read_access_3 = RISCAccess3 & ~RISCAccess_q2 & ~RW;
|
assign CpuStall_read_access_3 = CPUAccess3 & ~CPUAccess_q2 & ~RW;
|
assign RiscStall_access = (RISCAccess0 | RISCAccess1 | RISCAccess2 | RISCAccess3) & ~RISCAccess_q3;
|
assign CpuStall_access = (CPUAccess0 | CPUAccess1 | CPUAccess2 | CPUAccess3) & ~CPUAccess_q3;
|
|
|
|
|
reg wb_Access_wbClk_q;
|
reg wb_Access_wbClk_q;
|
// Delayed signals used for accessing WISHBONE
|
// Delayed signals used for accessing WISHBONE
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
| Line 869... |
Line 900... |
WBInProgress_sync1<=#Tp WBInProgress;
|
WBInProgress_sync1<=#Tp WBInProgress;
|
WBInProgress_tck<=#Tp WBInProgress_sync1;
|
WBInProgress_tck<=#Tp WBInProgress_sync1;
|
end
|
end
|
|
|
|
|
// Whan enabled, TRACE stalls RISC while saving data to the trace buffer.
|
// Whan enabled, TRACE stalls CPU while saving data to the trace buffer.
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
assign risc_stall_o = RiscStall_access | RiscStall_reg | RiscStall_trace ;
|
assign cpu_stall_o = CpuStall_access | CpuStall_reg | CpuStall_trace ;
|
`else
|
`else
|
assign risc_stall_o = RiscStall_access | RiscStall_reg;
|
assign cpu_stall_o = CpuStall_access | CpuStall_reg;
|
`endif
|
`endif
|
|
|
assign reset_o = RiscReset_reg;
|
assign reset_o = CpuReset_reg;
|
|
|
|
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
always @ (RiscStall_write_access_0 or RiscStall_write_access_1 or
|
always @ (CpuStall_write_access_0 or CpuStall_write_access_1 or
|
RiscStall_write_access_2 or RiscStall_write_access_2 or
|
CpuStall_write_access_2 or CpuStall_write_access_2 or
|
RiscStall_read_access_0 or RiscStall_read_access_1 or
|
CpuStall_read_access_0 or CpuStall_read_access_1 or
|
RiscStall_read_access_2 or RiscStall_read_access_3 or opselect_trace)
|
CpuStall_read_access_2 or CpuStall_read_access_3 or opselect_trace)
|
`else
|
`else
|
always @ (RiscStall_write_access_0 or RiscStall_write_access_1 or
|
always @ (CpuStall_write_access_0 or CpuStall_write_access_1 or
|
RiscStall_write_access_2 or RiscStall_write_access_3 or
|
CpuStall_write_access_2 or CpuStall_write_access_3 or
|
RiscStall_read_access_0 or RiscStall_read_access_1 or
|
CpuStall_read_access_0 or CpuStall_read_access_1 or
|
RiscStall_read_access_2 or RiscStall_read_access_3)
|
CpuStall_read_access_2 or CpuStall_read_access_3)
|
`endif
|
`endif
|
begin
|
begin
|
if(RiscStall_write_access_0)
|
if(CpuStall_write_access_0)
|
opselect_o = `DEBUG_WRITE_0;
|
opselect_o = `DEBUG_WRITE_0;
|
else
|
else
|
if(RiscStall_read_access_0)
|
if(CpuStall_read_access_0)
|
opselect_o = `DEBUG_READ_0;
|
opselect_o = `DEBUG_READ_0;
|
else
|
else
|
if(RiscStall_write_access_1)
|
if(CpuStall_write_access_1)
|
opselect_o = `DEBUG_WRITE_1;
|
opselect_o = `DEBUG_WRITE_1;
|
else
|
else
|
if(RiscStall_read_access_1)
|
if(CpuStall_read_access_1)
|
opselect_o = `DEBUG_READ_1;
|
opselect_o = `DEBUG_READ_1;
|
else
|
else
|
if(RiscStall_write_access_2)
|
if(CpuStall_write_access_2)
|
opselect_o = `DEBUG_WRITE_2;
|
opselect_o = `DEBUG_WRITE_2;
|
else
|
else
|
if(RiscStall_read_access_2)
|
if(CpuStall_read_access_2)
|
opselect_o = `DEBUG_READ_2;
|
opselect_o = `DEBUG_READ_2;
|
else
|
else
|
if(RiscStall_write_access_3)
|
if(CpuStall_write_access_3)
|
opselect_o = `DEBUG_WRITE_3;
|
opselect_o = `DEBUG_WRITE_3;
|
else
|
else
|
if(RiscStall_read_access_3)
|
if(CpuStall_read_access_3)
|
opselect_o = `DEBUG_READ_3;
|
opselect_o = `DEBUG_READ_3;
|
else
|
else
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
opselect_o = opselect_trace;
|
opselect_o = opselect_trace;
|
`else
|
`else
|
opselect_o = 3'h0;
|
opselect_o = 3'h0;
|
`endif
|
`endif
|
end
|
end
|
|
|
|
|
// Latching data read from RISC or registers
|
// Latching data read from CPU or registers
|
always @ (posedge risc_clk_i or posedge wb_rst_i)
|
always @ (posedge cpu_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
DataReadLatch[31:0]<=#Tp 0;
|
DataReadLatch[31:0]<=#Tp 0;
|
else
|
else
|
if(RISCAccess_q & ~RISCAccess_q2)
|
if(CPUAccess_q & ~CPUAccess_q2)
|
DataReadLatch[31:0]<=#Tp risc_data_i[31:0];
|
DataReadLatch[31:0]<=#Tp cpu_data_i[31:0];
|
else
|
else
|
if(RegAccess_q & ~RegAccess_q2)
|
if(RegAccess_q & ~RegAccess_q2)
|
DataReadLatch[31:0]<=#Tp RegDataIn[31:0];
|
DataReadLatch[31:0]<=#Tp RegDataIn[31:0];
|
end
|
end
|
|
|
assign risc_addr_o = ADDR;
|
assign cpu_addr_o = ADDR;
|
assign risc_data_o = DataOut;
|
assign cpu_data_o = DataOut;
|
|
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
| Line 949... |
Line 980... |
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
|
|
|
|
// Synchronizing the trace read buffer signal to risc_clk_i clock
|
// Synchronizing the trace read buffer signal to cpu_clk_i clock
|
dbg_sync_clk1_clk2 syn4 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
dbg_sync_clk1_clk2 syn4 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
.set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
|
.set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
|
);
|
);
|
|
|
|
|
|
|
always @(posedge risc_clk_i or posedge wb_rst_i)
|
always @(posedge cpu_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
ReadTraceBuffer_q <=#Tp 0;
|
ReadTraceBuffer_q <=#Tp 0;
|
else
|
else
|
ReadTraceBuffer_q <=#Tp ReadTraceBuffer;
|
ReadTraceBuffer_q <=#Tp ReadTraceBuffer;
|
| Line 1013... |
Line 1044... |
* *
|
* *
|
* Connecting Registers *
|
* Connecting Registers *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
dbg_registers dbgregs(.data_in(DataOut[31:0]), .data_out(RegDataIn[31:0]),
|
dbg_registers dbgregs(.data_in(DataOut[31:0]), .data_out(RegDataIn[31:0]),
|
.address(ADDR[4:0]), .rw(RW), .access(RegAccess & ~RegAccess_q), .clk(risc_clk_i),
|
.address(ADDR[4:0]), .rw(RW), .access(RegAccess & ~RegAccess_q), .clk(cpu_clk_i),
|
.bp(bp_i), .reset(wb_rst_i),
|
.bp(bp_i), .reset(wb_rst_i),
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
.ContinMode(ContinMode), .TraceEnable(TraceEnable),
|
.ContinMode(ContinMode), .TraceEnable(TraceEnable),
|
.WpTrigger(WpTrigger), .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger),
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.WpTrigger(WpTrigger), .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger),
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.ITrigger(ITrigger), .TriggerOper(TriggerOper), .WpQualif(WpQualif),
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.ITrigger(ITrigger), .TriggerOper(TriggerOper), .WpQualif(WpQualif),
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| Line 1033... |
Line 1064... |
.IQualifValid(IQualifValid),
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.IQualifValid(IQualifValid),
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.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
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.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
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.StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
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.StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
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.LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
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.LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
|
`endif
|
`endif
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.risc_stall(RiscStall_reg), .risc_stall_all(risc_stall_all_o), .risc_sel(risc_sel_o),
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.cpu_stall(CpuStall_reg), .cpu_stall_all(cpu_stall_all_o), .cpu_sel(cpu_sel_o),
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.risc_reset(RiscReset_reg), .mon_cntl_o(mon_cntl_o), .wb_cntl_o(wb_cntl_o)
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.cpu_reset(CpuReset_reg), .mon_cntl_o(mon_cntl_o), .wb_cntl_o(wb_cntl_o)
|
|
|
);
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);
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|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
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| Line 1052... |
Line 1083... |
* Connecting CRC module *
|
* Connecting CRC module *
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* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
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wire AsyncResetCrc = trst;
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wire AsyncResetCrc = trst;
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wire SyncResetCrc = UpdateDR_q;
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wire SyncResetCrc = UpdateDR_q;
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wire [7:0] CalculatedCrcIn; // crc calculated from the input data (shifted in)
|
|
|
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assign BitCounter_Lt4 = BitCounter<4;
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assign BitCounter_Lt4 = BitCounter<4;
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assign BitCounter_Eq5 = BitCounter==5;
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assign BitCounter_Eq5 = BitCounter==5;
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assign BitCounter_Eq32 = BitCounter==32;
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assign BitCounter_Eq32 = BitCounter==32;
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assign BitCounter_Lt38 = BitCounter<38;
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assign BitCounter_Lt38 = BitCounter<38;
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| Line 1065... |
Line 1095... |
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
assign BitCounter_Lt40 = BitCounter<40;
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assign BitCounter_Lt40 = BitCounter<40;
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`endif
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`endif
|
|
|
|
|
wire EnableCrcIn = ShiftDR &
|
// wire EnableCrcIn = ShiftDR &
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( (CHAIN_SELECTSelected & BitCounter_Lt4) |
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// ( (CHAIN_SELECTSelected & BitCounter_Lt4) |
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((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
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// ((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
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((DEBUGSelected & RiscDebugScanChain0) & BitCounter_Lt65)|
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// ((DEBUGSelected & CpuDebugScanChain0) & BitCounter_Lt65)|
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((DEBUGSelected & RiscDebugScanChain1) & BitCounter_Lt65)|
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// ((DEBUGSelected & CpuDebugScanChain1) & BitCounter_Lt65)|
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((DEBUGSelected & RiscDebugScanChain2) & BitCounter_Lt65)|
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// ((DEBUGSelected & CpuDebugScanChain2) & BitCounter_Lt65)|
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((DEBUGSelected & RiscDebugScanChain3) & BitCounter_Lt65)|
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// ((DEBUGSelected & CpuDebugScanChain3) & BitCounter_Lt65)|
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((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
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// ((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
|
);
|
// );
|
|
|
wire EnableCrcOut= ShiftDR &
|
wire EnableCrc = ShiftDR &
|
(
|
( (CHAIN_SELECTSelected & BitCounter_Lt4) |
|
((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
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((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
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((DEBUGSelected & RiscDebugScanChain0) & BitCounter_Lt65)|
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((DEBUGSelected & CpuDebugScanChain0) & BitCounter_Lt65)|
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((DEBUGSelected & RiscDebugScanChain1) & BitCounter_Lt65)|
|
((DEBUGSelected & CpuDebugScanChain1) & BitCounter_Lt65)|
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((DEBUGSelected & RiscDebugScanChain2) & BitCounter_Lt65)|
|
((DEBUGSelected & CpuDebugScanChain2) & BitCounter_Lt65)|
|
((DEBUGSelected & RiscDebugScanChain3) & BitCounter_Lt65)|
|
((DEBUGSelected & CpuDebugScanChain3) & BitCounter_Lt65)|
|
((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
|
((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
|
|
|
|
((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
|
((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
|
`endif
|
`endif
|
);
|
);
|
|
|
|
// wire EnableCrcOut= ShiftDR &
|
|
// (
|
|
// ((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
|
|
// ((DEBUGSelected & CpuDebugScanChain0) & BitCounter_Lt65)|
|
|
// ((DEBUGSelected & CpuDebugScanChain1) & BitCounter_Lt65)|
|
|
// ((DEBUGSelected & CpuDebugScanChain2) & BitCounter_Lt65)|
|
|
// ((DEBUGSelected & CpuDebugScanChain3) & BitCounter_Lt65)|
|
|
// ((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
|
|
// `ifdef TRACE_ENABLED
|
|
// |
|
|
// ((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
|
|
// `endif
|
|
// );
|
|
|
// Calculating crc for input data
|
// Calculating crc for input data
|
dbg_crc8_d1 crc1 (.data(tdi), .enable_crc(EnableCrcIn), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
|
//dbg_crc8_d1 crc1 (.data(tdi), .enable_crc(EnableCrcIn), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
|
|
dbg_crc8_d1 crc1 (.data(tdi), .enable_crc(EnableCrc), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
|
.crc_out(CalculatedCrcIn), .clk(tck));
|
.crc_out(CalculatedCrcIn), .clk(tck));
|
|
|
// Calculating crc for output data
|
// Calculating crc for output data
|
dbg_crc8_d1 crc2 (.data(TDOData), .enable_crc(EnableCrcOut), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
|
//dbg_crc8_d1 crc2 (.data(TDOData), .enable_crc(EnableCrcOut), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
|
|
dbg_crc8_d1 crc2 (.data(TDOData), .enable_crc(EnableCrc), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
|
.crc_out(CalculatedCrcOut), .clk(tck));
|
.crc_out(CalculatedCrcOut), .clk(tck));
|
|
|
|
|
// Generating CrcMatch signal
|
reg [3:0] crc_cnt;
|
always @ (posedge tck or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
CrcMatch <=#Tp 1'b0;
|
crc_cnt <= 0;
|
else
|
else if (Exit1DR)
|
if(Exit1DR)
|
crc_cnt <=#Tp 0;
|
|
// else if ((~EnableCrcIn) & ShiftDR)
|
|
else if ((~EnableCrc) & ShiftDR)
|
|
crc_cnt <=#Tp crc_cnt + 1'b1;
|
|
end
|
|
|
|
|
|
// Generating CrcMatch signal.
|
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(CHAIN_SELECTSelected)
|
if(trst)
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[11:4];
|
CrcMatch <=#Tp 1'b1;
|
else
|
else if (SelectDRScan)
|
|
CrcMatch <=#Tp 1'b1;
|
|
// else if ((~EnableCrcIn) & ShiftDR)
|
|
else if ((~EnableCrc) & ShiftDR)
|
begin
|
begin
|
if(RegisterScanChain)
|
if (tdi != CalculatedCrcIn[crc_cnt])
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[45:38];
|
CrcMatch <=#Tp 1'b0;
|
else
|
|
if(RiscDebugScanChain0 | RiscDebugScanChain1 | RiscDebugScanChain2 | RiscDebugScanChain3)
|
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
|
|
else
|
|
if(WishboneScanChain)
|
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
|
|
end
|
end
|
end
|
end
|
|
|
|
|
|
// Generating CrcMatch_q signal.
|
|
always @ (posedge tck or posedge trst)
|
|
begin
|
|
CrcMatch_q <=#Tp CrcMatch;
|
end
|
end
|
|
|
|
|
// Active chain
|
// Active chain
|
assign RegisterScanChain = Chain == `REGISTER_SCAN_CHAIN;
|
assign RegisterScanChain = Chain == `REGISTER_SCAN_CHAIN;
|
assign RiscDebugScanChain0 = Chain == `RISC_DEBUG_CHAIN_0;
|
assign CpuDebugScanChain0 = Chain == `CPU_DEBUG_CHAIN_0;
|
assign RiscDebugScanChain1 = Chain == `RISC_DEBUG_CHAIN_1;
|
assign CpuDebugScanChain1 = Chain == `CPU_DEBUG_CHAIN_1;
|
assign RiscDebugScanChain2 = Chain == `RISC_DEBUG_CHAIN_2;
|
assign CpuDebugScanChain2 = Chain == `CPU_DEBUG_CHAIN_2;
|
assign RiscDebugScanChain3 = Chain == `RISC_DEBUG_CHAIN_3;
|
assign CpuDebugScanChain3 = Chain == `CPU_DEBUG_CHAIN_3;
|
assign WishboneScanChain = Chain == `WISHBONE_SCAN_CHAIN;
|
assign WishboneScanChain = Chain == `WISHBONE_SCAN_CHAIN;
|
|
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
assign TraceTestScanChain = Chain == `TRACE_TEST_CHAIN;
|
assign TraceTestScanChain = Chain == `TRACE_TEST_CHAIN;
|
`endif
|
`endif
|
| Line 1147... |
Line 1204... |
* *
|
* *
|
* Connecting trace module *
|
* Connecting trace module *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(risc_data_i), .OpSelect(opselect_trace),
|
dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(cpu_data_i), .OpSelect(opselect_trace),
|
.LsStatus(lsstatus_i), .IStatus(istatus_i), .RiscStall_O(RiscStall_trace),
|
.LsStatus(lsstatus_i), .IStatus(istatus_i), .CpuStall_O(CpuStall_trace),
|
.Mclk(risc_clk_i), .Reset(wb_rst_i), .TraceChain(TraceChain),
|
.Mclk(cpu_clk_i), .Reset(wb_rst_i), .TraceChain(TraceChain),
|
.ContinMode(ContinMode), .TraceEnable_reg(TraceEnable),
|
.ContinMode(ContinMode), .TraceEnable_reg(TraceEnable),
|
.WpTrigger(WpTrigger),
|
.WpTrigger(WpTrigger),
|
.BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
|
.BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
|
.TriggerOper(TriggerOper), .WpQualif(WpQualif), .BpQualif(BpQualif),
|
.TriggerOper(TriggerOper), .WpQualif(WpQualif), .BpQualif(BpQualif),
|
.LSSQualif(LSSQualif), .IQualif(IQualif), .QualifOper(QualifOper),
|
.LSSQualif(LSSQualif), .IQualif(IQualif), .QualifOper(QualifOper),
|
