Subversion Repositories dbg_interface

// Enable TRACE

//`define TRACE_ENABLED  // Uncomment this define to activate the trace

// Define number of cpus supported by the dbg interface

`define CPU_NUM 2

// Define master clock (CPU clock)

//`define       CPU_CLOCK  50   // Half period = 50 ns => MCLK = 10 Mhz

`define CPU_CLOCK  2.5   // Half period = 5 ns => MCLK = 200 Mhz

// Trace buffer size and counter and write/read pointer width. This can be expanded when more RAM is avaliable

`define TRACECOUNTERWIDTH        5

`define TRACEBUFFERLENGTH        32 // 2^5

`define TRACESAMPLEWIDTH         36

// OpSelect width

`define OPSELECTWIDTH            3

`define OPSELECTIONCOUNTER       8    //2^3

// OpSelect (dbg_op_i) signal meaning

`define DEBUG_READ_0               0

`define DEBUG_WRITE_0              1

`define DEBUG_READ_1               2

`define DEBUG_WRITE_1              3

`define DEBUG_READ_2               4

`define DEBUG_WRITE_2              5

`define DEBUG_READ_3               6

`define DEBUG_WRITE_3              7

// Registers addresses

`define MODER_ADR           5'h00

`define TSEL_ADR            5'h01

`define QSEL_ADR            5'h02

`define SSEL_ADR            5'h03

`define CPUOP_ADR           5'h04

`define CPUSEL_ADR          5'h05

`define RECSEL_ADR          5'h10

`define MON_CNTL_ADR        5'h11

`define WB_CNTL_ADR         5'h12

// Registers default values (after reset)

`define MODER_DEF           2'h0

`define TSEL_DEF            32'h00000000

`define QSEL_DEF            32'h00000000

`define SSEL_DEF            32'h00000000

`define CPUOP_DEF           2'h0

`define RECSEL_DEF          7'h0

`define MON_CNTL_DEF        4'h0