URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_13/] [sim/] [rtl_sim/] [run/] [run_sim.scr] - Diff between revs 85 and 99

Rev 85	Rev 99
Line 41...	Line 41...


`# RTL files`	`# RTL files`
`echo "../../../rtl/verilog/dbg_crc32_d1.v" >> ncvlog.args`	`echo "../../../rtl/verilog/dbg_crc32_d1.v" >> ncvlog.args`
`echo "../../../rtl/verilog/dbg_wb.v" >> ncvlog.args`	`echo "../../../rtl/verilog/dbg_wb.v" >> ncvlog.args`
	`echo "../../../rtl/verilog/dbg_register.v" >> ncvlog.args`
	`echo "../../../rtl/verilog/dbg_cpu_registers.v" >> ncvlog.args`
	`echo "../../../rtl/verilog/dbg_cpu.v" >> ncvlog.args`
`echo "../../../rtl/verilog/dbg_top.v" >> ncvlog.args`	`echo "../../../rtl/verilog/dbg_top.v" >> ncvlog.args`
`echo "../../../../jtag/tap/rtl/verilog/tap_top.v" >> ncvlog.args`	`echo "../../../../jtag/tap/rtl/verilog/tap_top.v" >> ncvlog.args`


`# Simulation files`	`# Simulation files`