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//// All additional information is avaliable in the README.txt ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 - 2003 Authors ////
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//// Copyright (C) 2000 - 2004 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.25 2004/01/16 14:51:24 mohor
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// cpu registers added.
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//
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// Revision 1.24 2004/01/15 10:47:13 mohor
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// Revision 1.24 2004/01/15 10:47:13 mohor
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// Working.
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// Working.
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//
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//
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// Revision 1.23 2004/01/14 22:59:01 mohor
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// Revision 1.23 2004/01/14 22:59:01 mohor
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// Temp version.
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// Temp version.
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Line 131... |
Line 134... |
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`include "timescale.v"
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`include "timescale.v"
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`include "dbg_defines.v"
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`include "dbg_defines.v"
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`include "dbg_wb_defines.v"
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`include "dbg_wb_defines.v"
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`include "dbg_cpu_defines.v"
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`include "dbg_cpu_defines.v"
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//`include "dbg_tb_defines.v"
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// Test bench
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// Test bench
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module dbg_tb;
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module dbg_tb;
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parameter TCLK = 50; // Clock half period (Clok period = 100 ns => 10 MHz)
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parameter TCLK = 50; // Clock half period (Clok period = 100 ns => 10 MHz)
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wire wb_cab_o;
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wire wb_cab_o;
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wire wb_err_i;
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wire wb_err_i;
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wire [2:0] wb_cti_o;
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wire [2:0] wb_cti_o;
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wire [1:0] wb_bte_o;
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wire [1:0] wb_bte_o;
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// CPU signals
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wire cpu_clk_i;
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wire [31:0] cpu_addr_o;
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wire [31:0] cpu_data_i;
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wire [31:0] cpu_data_o;
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wire cpu_bp_i;
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wire cpu_stall_o;
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wire cpu_stall_all_o;
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wire cpu_stb_o;
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wire [`CPU_NUM -1:0] cpu_sel_o;
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wire cpu_we_o;
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wire cpu_ack_i;
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wire cpu_rst_o;
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// Text used for easier debugging
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// Text used for easier debugging
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reg [199:0] test_text;
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reg [199:0] test_text;
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reg [2:0] last_wb_cmd;
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reg [2:0] last_wb_cmd;
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reg [199:0] last_wb_cmd_text;
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reg [199:0] last_wb_cmd_text;
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reg [31:0] wb_data;
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reg [31:0] wb_data;
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.wb_we_o (wb_we_o),
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.wb_we_o (wb_we_o),
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.wb_ack_i (wb_ack_i),
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.wb_ack_i (wb_ack_i),
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.wb_cab_o (wb_cab_o),
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.wb_cab_o (wb_cab_o),
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.wb_err_i (wb_err_i),
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.wb_err_i (wb_err_i),
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.wb_cti_o (wb_cti_o),
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.wb_cti_o (wb_cti_o),
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.wb_bte_o (wb_bte_o)
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.wb_bte_o (wb_bte_o),
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// CPU signals
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.cpu_clk_i (cpu_clk_i),
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.cpu_addr_o (cpu_addr_o),
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.cpu_data_i (cpu_data_i),
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.cpu_data_o (cpu_data_o),
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.cpu_bp_i (cpu_bp_i),
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.cpu_stall_o (cpu_stall_o),
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.cpu_stall_all_o (cpu_stall_all_o),
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.cpu_stb_o (cpu_stb_o),
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.cpu_sel_o (cpu_sel_o),
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.cpu_we_o (cpu_we_o),
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.cpu_ack_i (cpu_ack_i),
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.cpu_rst_o (cpu_rst_o)
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);
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);
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// Connecting CRC module that calculates CRC that is shifted into debug
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// Connecting CRC module that calculates CRC that is shifted into debug
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Line 334... |
.WE_I (wb_we_o),
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.WE_I (wb_we_o),
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.CAB_I(1'b0)
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.CAB_I(1'b0)
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);
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);
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cpu_behavioral i_cpu_behavioral
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(
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// CPU signals
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.cpu_rst_i (wb_rst_i),
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.cpu_clk_o (cpu_clk_i),
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.cpu_addr_i (cpu_addr_o),
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.cpu_data_o (cpu_data_i),
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.cpu_data_i (cpu_data_o),
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.cpu_bp_o (cpu_bp_i),
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.cpu_stall_i (cpu_stall_o),
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.cpu_stall_all_i (cpu_stall_all_o),
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.cpu_stb_i (cpu_stb_o),
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.cpu_sel_i (cpu_sel_o),
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.cpu_we_i (cpu_we_o),
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.cpu_ack_o (cpu_ack_i),
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.cpu_rst_o (cpu_rst_o)
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);
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// Initial values
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// Initial values
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initial
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initial
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begin
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begin
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test_enabled = 1'b0;
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test_enabled = 1'b0;
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crc_out_en = 1'b0;
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crc_out_en = 1'b0;
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Line 488... |
debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, result, "go 2"); // {command, ready, addr, length, gen_crc_err, result, text}
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debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, result, "go 2"); // {command, ready, addr, length, gen_crc_err, result, text}
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#10000;
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#10000;
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chain_select(`CPU_DEBUG_CHAIN, 1'b0); // {chain, gen_crc_err}
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chain_select(`CPU_DEBUG_CHAIN, 1'b0); // {chain, gen_crc_err}
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// Select cpu0
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#10000;
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debug_cpu(`CPU_WRITE_REG, `CPU_SEL_ADR, 32'h0, 1'b0, result, "select cpu 0"); // {command, addr, data, gen_crc_err, result, text}
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#10000;
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debug_cpu(`CPU_GO, 32'h0, 32'h1, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
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// Read register
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#10000;
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#10000;
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debug_cpu(`CPU_WRITE_REG, 32'h00000001, 32'h0, 1'b0, result, "cpu_write_reg"); // {command, addr, data, gen_crc_err, result, text}
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debug_cpu(`CPU_READ_REG, `CPU_SEL_ADR, 32'h0, 1'b0, result, "cpu_read_reg"); // {command, addr, data, gen_crc_err, result, text}
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#10000;
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#10000;
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debug_cpu(`CPU_GO, 32'h0, 32'hff, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
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debug_cpu(`CPU_GO, 32'h0, 32'hff, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
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// Stall cpu0
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#10000;
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debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "stall cpu0"); // {command, addr, data, gen_crc_err, result, text}
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#10000;
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debug_cpu(`CPU_GO, 32'h0, 32'h1, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
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// write to cpu 32-bit
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#10000;
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debug_cpu(`CPU_WRITE32, 32'h32323232, 32'h0, 1'b0, result, "cpu_write_32"); // {command, addr, data, gen_crc_err, result, text}
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#10000;
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debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
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// write from cpu 32-bit
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#10000;
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debug_cpu(`CPU_READ32, 32'h32323232, 32'h0, 1'b0, result, "cpu_read_32"); // {command, addr, data, gen_crc_err, result, text}
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#10000;
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debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
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// write to cpu 8-bit
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#10000;
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debug_cpu(`CPU_WRITE8, 32'h08080808, 32'h0, 1'b0, result, "cpu_write_8"); // {command, addr, data, gen_crc_err, result, text}
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#10000;
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debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
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// write from cpu 8-bit
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#10000;
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debug_cpu(`CPU_READ8, 32'h08080808, 32'h0, 1'b0, result, "cpu_read_8"); // {command, addr, data, gen_crc_err, result, text}
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#10000;
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debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
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/*
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/*
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// Testing read and write to CPU0 registers
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// Testing read and write to CPU0 registers
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#10000;
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#10000;
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set_instruction(`CHAIN_SELECT);
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set_instruction(`CHAIN_SELECT);
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