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[/] [dbg_interface/] [tags/] [rel_15/] [bench/] [verilog/] [dbg_tb.v] - Diff between revs 17 and 36

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Line 2... Line 2... 
////                                                              ////
 
////                                                              ////
 
////  dbg_tb.v                                                    ////
 
////  dbg_tb.v                                                    ////
 
////                                                              ////
 
////                                                              ////
 
////                                                              ////
 
////                                                              ////
 
////  This file is part of the SoC/OpenRISC Development Interface ////
 
////  This file is part of the SoC/OpenRISC Development Interface ////
 
////  http://www.opencores.org/cores/DebugInterface/              ////
 
////  http://www.opencores.org/projects/DebugInterface/           ////
 
////                                                              ////
 
////                                                              ////
 
////                                                              ////
 
////                                                              ////
 
////  Author(s):                                                  ////
 
////  Author(s):                                                  ////
 
////       Igor Mohor                                             ////
 
////       Igor Mohor                                             ////
 
////       igorm@opencores.org                                    ////
 
////       igorm@opencores.org                                    ////
Line 43... Line 43... 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
//
 
//
 
// $Log: not supported by cvs2svn $
 
// $Log: not supported by cvs2svn $
 
 
 
// Revision 1.9  2001/10/19 11:39:20  mohor
 
 
 
// dbg_timescale.v changed to timescale.v This is done for the simulation of
 
 
 
// few different cores in a single project.
 
 
 
//
 
// Revision 1.8  2001/10/17 10:39:17  mohor
 
// Revision 1.8  2001/10/17 10:39:17  mohor
 
// bs_chain_o added.
 
// bs_chain_o added.
 
//
 
//
 
// Revision 1.7  2001/10/16 10:10:18  mohor
 
// Revision 1.7  2001/10/16 10:10:18  mohor
 
// Signal names changed to lowercase.
 
// Signal names changed to lowercase.
Line 123... Line 127... 
wire        wb_cab_i;
 
wire        wb_cab_i;
 
reg         wb_err_o;
 
reg         wb_err_o;
 
 
 
 
 
 
 
 
 
// Connecting TAP module
 
// Connecting TAP module
 
dbg_top dbgTAP1(.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI),
 
tap_top i_tap_top
 
                .tdo_pad_o(P_TDO),
 
               (.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI),
 
                .capture_dr_o(), .shift_dr_o(), .update_dr_o(), .extest_selected_o(),
 
                .tdo_pad_o(P_TDO), .tdo_padoen_o(tdo_padoen_o),
 
                .bs_chain_i(1'b0), .bs_chain_o(),
 
 
 
 
 
 
 
 
 
 
 
                .wb_rst_i(wb_rst_i), .risc_clk_i(Mclk),
 
                .wb_rst_i(wb_rst_i), .risc_clk_i(Mclk),
 
                .risc_addr_o(ADDR_RISC), .risc_data_i(DATAOUT_RISC), .risc_data_o(DATAIN_RISC),
 
                .risc_addr_o(ADDR_RISC), .risc_data_i(DATAOUT_RISC), .risc_data_o(DATAIN_RISC),
 
                .wp_i(Wp), .bp_i(Bp),
 
                .wp_i(Wp), .bp_i(Bp),
 
                .opselect_o(OpSelect), .lsstatus_i(LsStatus), .istatus_i(IStatus),
 
                .opselect_o(OpSelect), .lsstatus_i(LsStatus), .istatus_i(IStatus),
Line 149... Line 151... 
 
 
 
 
 
 
 
 
initial
 
initial
 
begin
 
begin
 
  TestEnabled<=#Tp 0;
 
  TestEnabled<=#Tp 0;
 
  P_TMS<=#Tp 0;
 
  P_TMS<=#Tp 'hz;
 
  P_TCK<=#Tp 0;
 
  P_TCK<=#Tp 'hz;
 
  P_TDI<=#Tp 0;
 
  P_TDI<=#Tp 'hz;
 
 
 
 
 
  Wp<=#Tp 0;
 
  Wp<=#Tp 0;
 
  Bp<=#Tp 0;
 
  Bp<=#Tp 0;
 
  LsStatus<=#Tp 0;
 
  LsStatus<=#Tp 0;
 
  IStatus<=#Tp 0;
 
  IStatus<=#Tp 0;
Line 230... Line 232... 
//
 
//
 
 
 
 
 
 
 
 
 
// Testing read and write to internal registers
 
// Testing read and write to internal registers
 
  SetInstruction(`IDCODE);
 
  SetInstruction(`IDCODE);
 
  ReadIDCode;
 
  ReadIDCode; // muten
 
 
 
 
 
  SetInstruction(`CHAIN_SELECT);
 
  SetInstruction(`CHAIN_SELECT);
 
  ChainSelect(`REGISTER_SCAN_CHAIN, 8'h0e);  // {chain, crc}
 
  ChainSelect(`REGISTER_SCAN_CHAIN, 8'h0e);  // {chain, crc}
 
  SetInstruction(`DEBUG);
 
  SetInstruction(`DEBUG);
 
 
 
 
Line 286... Line 288... 
    #1000 WriteRegister(`QUALIFOP_OR | `BPQUALIFVALID | `BPQUALIF, `QSEL_ADR,   8'had);    // Any qualifier
 
    #1000 WriteRegister(`QUALIFOP_OR | `BPQUALIFVALID | `BPQUALIF, `QSEL_ADR,   8'had);    // Any qualifier
 
    #1000 WriteRegister(32'h00000000, `TSEL_ADR,   8'h06);    // Any trigger
 
    #1000 WriteRegister(32'h00000000, `TSEL_ADR,   8'h06);    // Any trigger
 
    #1000 WriteRegister(32'h0000000c, `RECSEL_ADR,   8'h0f);  // Two samples are selected for recording (RECSDATA and RECLDATA)
 
    #1000 WriteRegister(32'h0000000c, `RECSEL_ADR,   8'h0f);  // Two samples are selected for recording (RECSDATA and RECLDATA)
 
    #1000 WriteRegister(32'h00000000, `SSEL_ADR,   8'h34);    // No stop signal
 
    #1000 WriteRegister(32'h00000000, `SSEL_ADR,   8'h34);    // No stop signal
 
    #1000 WriteRegister(`ENABLE, `MODER_ADR,    8'hd4);       // Trace enabled
 
    #1000 WriteRegister(`ENABLE, `MODER_ADR,    8'hd4);       // Trace enabled
 
    wait(dbg_tb.dbgTAP1.TraceEnable)
 
    wait(dbg_tb.i_tap_top.TraceEnable)
 
    @ (posedge Mclk);
 
    @ (posedge Mclk);
 
      #1 Bp = 1;                                                 // Set breakpoint
 
      #1 Bp = 1;                                                 // Set breakpoint
 
    repeat(8) @(posedge Mclk);
 
    repeat(8) @(posedge Mclk);
 
    wait(dbg_tb.dbgTAP1.dbgTrace1.RiscStall)
 
    wait(dbg_tb.i_tap_top.dbgTrace1.RiscStall)
 
      #1 Bp = 0;                                                 // Clear breakpoint
 
      #1 Bp = 0;                                                 // Clear breakpoint
 
// End: Anything starts trigger, breakpoint starts qualifier */
 
// End: Anything starts trigger, breakpoint starts qualifier */
 
 
 
 
 
 
 
 
 
/* Anything starts qualifier, breakpoint starts trigger
 
/* Anything starts qualifier, breakpoint starts trigger
Line 302... Line 304... 
    #1000 WriteRegister(32'h00000000, `QSEL_ADR,   8'h50);    // Any qualifier
 
    #1000 WriteRegister(32'h00000000, `QSEL_ADR,   8'h50);    // Any qualifier
 
    #1000 WriteRegister(`LSSTRIG_0 | `LSSTRIG_2 | `LSSTRIGVALID | `WPTRIG_4 | `WPTRIGVALID | `TRIGOP_AND, `TSEL_ADR,   8'had);    // Trigger is AND of Watchpoint4 and LSSTRIG[0] and LSSTRIG[2]
 
    #1000 WriteRegister(`LSSTRIG_0 | `LSSTRIG_2 | `LSSTRIGVALID | `WPTRIG_4 | `WPTRIGVALID | `TRIGOP_AND, `TSEL_ADR,   8'had);    // Trigger is AND of Watchpoint4 and LSSTRIG[0] and LSSTRIG[2]
 
    #1000 WriteRegister(32'h00000003, `RECSEL_ADR,   8'h0c);  // Two samples are selected for recording (RECPC and RECLSEA)
 
    #1000 WriteRegister(32'h00000003, `RECSEL_ADR,   8'h0c);  // Two samples are selected for recording (RECPC and RECLSEA)
 
    #1000 WriteRegister(32'h00000000, `SSEL_ADR,   8'h34);    // No stop signal
 
    #1000 WriteRegister(32'h00000000, `SSEL_ADR,   8'h34);    // No stop signal
 
    #1000 WriteRegister(`ENABLE, `MODER_ADR,    8'hd4);       // Trace enabled
 
    #1000 WriteRegister(`ENABLE, `MODER_ADR,    8'hd4);       // Trace enabled
 
    wait(dbg_tb.dbgTAP1.TraceEnable)
 
    wait(dbg_tb.i_tap_top.TraceEnable)
 
    @ (posedge Mclk)
 
    @ (posedge Mclk)
 
      Wp[4] = 1;                                              // Set watchpoint[4]
 
      Wp[4] = 1;                                              // Set watchpoint[4]
 
      LsStatus = 4'h5;                                        // LsStatus[0] and LsStatus[2] are active
 
      LsStatus = 4'h5;                                        // LsStatus[0] and LsStatus[2] are active
 
    @ (posedge Mclk)
 
    @ (posedge Mclk)
 
      Wp[4] = 0;                                              // Clear watchpoint[4]
 
      Wp[4] = 0;                                              // Clear watchpoint[4]
Line 424... Line 426... 
    begin
 
    begin
 
      P_TDI<=#Tp Data[i];
 
      P_TDI<=#Tp Data[i];
 
      GenClk(1);
 
      GenClk(1);
 
    end
 
    end
 
 
 
 
 
    for(i=0; i<`CRC_LENGTH-1; i=i+1)
 
//    for(i=0; i<`CRC_LENGTH-1; i=i+1)
 
 
 
    for(i=0; i<`CRC_LENGTH; i=i+1)      // +1 because crc is 9 bit long
 
    begin
 
    begin
 
      P_TDI<=#Tp Crc[i];
 
      P_TDI<=#Tp Crc[i];
 
      GenClk(1);
 
      GenClk(1);
 
    end
 
    end
 
 
 
 
 
    P_TDI<=#Tp Crc[i]; // last shift
 
//    P_TDI<=#Tp Crc[i]; // last shift
 
 
 
    P_TDI<=#Tp 1'b0;     // Crc[i]; // last shift
 
    P_TMS<=#Tp 1;        // going out of shiftIR
 
    P_TMS<=#Tp 1;        // going out of shiftIR
 
    GenClk(1);
 
    GenClk(1);
 
      P_TDI<=#Tp 'hz; // tri-state
 
      P_TDI<=#Tp 'hz; // tri-state
 
    GenClk(1);
 
    GenClk(1);
 
    P_TMS<=#Tp 0;
 
    P_TMS<=#Tp 0;
Line 451... Line 455... 
    P_TMS<=#Tp 0;
 
    P_TMS<=#Tp 0;
 
    GenClk(2);  // we are in shiftDR
 
    GenClk(2);  // we are in shiftDR
 
 
 
 
 
    P_TDI<=#Tp 0;
 
    P_TDI<=#Tp 0;
 
    GenClk(31);
 
    GenClk(31);
 
 
 
 
 
    P_TMS<=#Tp 1;        // going out of shiftIR
 
    P_TMS<=#Tp 1;        // going out of shiftIR
 
    GenClk(1);
 
    GenClk(1);
 
 
 
 
 
      P_TDI<=#Tp 'hz; // tri-state
 
      P_TDI<=#Tp 'hz; // tri-state
 
    GenClk(1);
 
    GenClk(1);
 
    P_TMS<=#Tp 0;
 
    P_TMS<=#Tp 0;
 
    GenClk(1);       // we are in RunTestIdle
 
    GenClk(1);       // we are in RunTestIdle
 
  end
 
  end
Line 508... Line 514... 
    begin
 
    begin
 
      P_TDI<=#Tp 0;     // Shifting data. Data is not important in read cycle.
 
      P_TDI<=#Tp 0;     // Shifting data. Data is not important in read cycle.
 
      GenClk(1);
 
      GenClk(1);
 
    end
 
    end
 
 
 
 
 
    for(i=0; i<`CRC_LENGTH-1; i=i+1)
 
//    for(i=0; i<`CRC_LENGTH-1; i=i+1)
 
 
 
    for(i=0; i<`CRC_LENGTH; i=i+1)      // crc is 9 bit long
 
    begin
 
    begin
 
      P_TDI<=#Tp Crc[i];     // Shifting CRC.
 
      P_TDI<=#Tp Crc[i];     // Shifting CRC.
 
      GenClk(1);
 
      GenClk(1);
 
    end
 
    end
 
 
 
 
 
    P_TDI<=#Tp Crc[i];   // Shifting last bit of CRC.
 
//    P_TDI<=#Tp Crc[i];   // Shifting last bit of CRC.
 
 
 
    P_TDI<=#Tp 1'b0;       // Crc[i];   // Shifting last bit of CRC.
 
    P_TMS<=#Tp 1;        // going out of shiftIR
 
    P_TMS<=#Tp 1;        // going out of shiftIR
 
    GenClk(1);
 
    GenClk(1);
 
      P_TDI<=#Tp 'hz;   // Tristate TDI.
 
      P_TDI<=#Tp 'hz;   // Tristate TDI.
 
    GenClk(1);
 
    GenClk(1);
 
 
 
 
Line 554... Line 562... 
    begin
 
    begin
 
      P_TDI<=#Tp Data[i];     // Shifting data
 
      P_TDI<=#Tp Data[i];     // Shifting data
 
      GenClk(1);
 
      GenClk(1);
 
    end
 
    end
 
 
 
 
 
    for(i=0; i<`CRC_LENGTH-1; i=i+1)
 
//    for(i=0; i<`CRC_LENGTH-1; i=i+1)
 
 
 
    for(i=0; i<`CRC_LENGTH; i=i+1)      // crc is 9 bit long
 
    begin
 
    begin
 
      P_TDI<=#Tp Crc[i];     // Shifting CRC
 
      P_TDI<=#Tp Crc[i];     // Shifting CRC
 
      GenClk(1);
 
      GenClk(1);
 
    end
 
    end
 
 
 
 
 
    P_TDI<=#Tp Crc[i];        // shifting last bit of CRC
 
//    P_TDI<=#Tp Crc[i];        // shifting last bit of CRC
 
 
 
    P_TDI<=#Tp 1'b0;            // Crc[i];        // shifting last bit of CRC
 
    P_TMS<=#Tp 1;        // going out of shiftIR
 
    P_TMS<=#Tp 1;        // going out of shiftIR
 
    GenClk(1);
 
    GenClk(1);
 
      P_TDI<=#Tp 'hz;        // tristate TDI
 
      P_TDI<=#Tp 'hz;        // tristate TDI
 
    GenClk(1);
 
    GenClk(1);
 
 
 
 
Line 601... Line 611... 
    begin
 
    begin
 
      P_TDI<=#Tp 0;     // Shifting data. Data is not important in read cycle.
 
      P_TDI<=#Tp 0;     // Shifting data. Data is not important in read cycle.
 
      GenClk(1);
 
      GenClk(1);
 
    end
 
    end
 
 
 
 
 
    for(i=0; i<`CRC_LENGTH-1; i=i+1)
 
//    for(i=0; i<`CRC_LENGTH-1; i=i+1)
 
 
 
    for(i=0; i<`CRC_LENGTH; i=i+1)      // crc is 9 bit long
 
    begin
 
    begin
 
      P_TDI<=#Tp Crc[i];     // Shifting CRC. CRC is not important in read cycle.
 
      P_TDI<=#Tp Crc[i];     // Shifting CRC. CRC is not important in read cycle.
 
      GenClk(1);
 
      GenClk(1);
 
    end
 
    end
 
 
 
 
 
    P_TDI<=#Tp Crc[i];     // Shifting last bit of CRC.
 
//    P_TDI<=#Tp Crc[i];     // Shifting last bit of CRC.
 
 
 
    P_TDI<=#Tp 1'b0;         // Crc[i];     // Shifting last bit of CRC.
 
    P_TMS<=#Tp 1;        // going out of shiftIR
 
    P_TMS<=#Tp 1;        // going out of shiftIR
 
    GenClk(1);
 
    GenClk(1);
 
      P_TDI<=#Tp 'hz;     // Tri state TDI
 
      P_TDI<=#Tp 'hz;     // Tri state TDI
 
    GenClk(1);
 
    GenClk(1);
 
    P_TMS<=#Tp 0;
 
    P_TMS<=#Tp 0;
Line 648... Line 660... 
    begin
 
    begin
 
      P_TDI<=#Tp Data[i];     // Shifting data
 
      P_TDI<=#Tp Data[i];     // Shifting data
 
      GenClk(1);
 
      GenClk(1);
 
    end
 
    end
 
 
 
 
 
    for(i=0; i<`CRC_LENGTH-1; i=i+1)
 
//    for(i=0; i<`CRC_LENGTH-1; i=i+1)
 
 
 
    for(i=0; i<`CRC_LENGTH; i=i+1)      // crc is 9 bit long
 
    begin
 
    begin
 
      P_TDI<=#Tp Crc[i];     // Shifting CRC
 
      P_TDI<=#Tp Crc[i];     // Shifting CRC
 
      GenClk(1);
 
      GenClk(1);
 
    end
 
    end
 
 
 
 
 
    P_TDI<=#Tp Crc[i];   // Shifting last bit of CRC
 
//    P_TDI<=#Tp Crc[i];   // Shifting last bit of CRC
 
 
 
    P_TDI<=#Tp 1'b0;       // Crc[i];   // Shifting last bit of CRC
 
    P_TMS<=#Tp 1;        // going out of shiftIR
 
    P_TMS<=#Tp 1;        // going out of shiftIR
 
    GenClk(1);
 
    GenClk(1);
 
      P_TDI<=#Tp 'hz;   // Tri state TDI
 
      P_TDI<=#Tp 'hz;   // Tri state TDI
 
    GenClk(1);
 
    GenClk(1);
 
 
 
 
Line 717... Line 731... 
 
 
 
 
// Print samples that are recorded to the trace buffer
 
// Print samples that are recorded to the trace buffer
 
`ifdef TRACE_ENABLED
 
`ifdef TRACE_ENABLED
 
always @ (posedge Mclk)
 
always @ (posedge Mclk)
 
begin
 
begin
 
  if(dbg_tb.dbgTAP1.dbgTrace1.WriteSample)
 
  if(dbg_tb.i_tap_top.dbgTrace1.WriteSample)
 
    $write("\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWritten to Trace buffer: WritePointer=0x%x, Data=0x%x", dbg_tb.dbgTAP1.dbgTrace1.WritePointer, {dbg_tb.dbgTAP1.dbgTrace1.DataIn, 1'b0, dbg_tb.dbgTAP1.dbgTrace1.OpSelect[`OPSELECTWIDTH-1:0]});
 
    $write("\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWritten to Trace buffer: WritePointer=0x%x, Data=0x%x", dbg_tb.i_tap_top.dbgTrace1.WritePointer, {dbg_tb.i_tap_top.dbgTrace1.DataIn, 1'b0, dbg_tb.i_tap_top.dbgTrace1.OpSelect[`OPSELECTWIDTH-1:0]});
 
end
 
end
 
`endif
 
`endif
 
 
 
 
 
 
 
 
 
// Print selected instruction
 
// Print selected instruction
 
reg UpdateIR_q;
 
reg UpdateIR_q;
 
always @ (posedge P_TCK)
 
always @ (posedge P_TCK)
 
begin
 
begin
 
  UpdateIR_q<=#Tp dbg_tb.dbgTAP1.UpdateIR;
 
  UpdateIR_q<=#Tp dbg_tb.i_tap_top.UpdateIR;
 
end
 
end
 
 
 
 
 
always @ (posedge P_TCK)
 
always @ (posedge P_TCK)
 
begin
 
begin
 
  if(UpdateIR_q)
 
  if(UpdateIR_q)
 
    case(dbg_tb.dbgTAP1.JTAG_IR[`IR_LENGTH-1:0])
 
    case(dbg_tb.i_tap_top.JTAG_IR[`IR_LENGTH-1:0])
 
      `EXTEST         : $write("\n\tInstruction EXTEST");
 
      `EXTEST         : $write("\n\tInstruction EXTEST");
 
      `SAMPLE_PRELOAD : $write("\n\tInstruction SAMPLE_PRELOAD");
 
      `SAMPLE_PRELOAD : $write("\n\tInstruction SAMPLE_PRELOAD");
 
      `IDCODE         : $write("\n\tInstruction IDCODE");
 
      `IDCODE         : $write("\n\tInstruction IDCODE");
 
      `CHAIN_SELECT   : $write("\n\tInstruction CHAIN_SELECT");
 
      `CHAIN_SELECT   : $write("\n\tInstruction CHAIN_SELECT");
 
      `INTEST         : $write("\n\tInstruction INTEST");
 
      `INTEST         : $write("\n\tInstruction INTEST");
Line 753... Line 767... 
 
 
 
 
 
 
 
 
// Print selected chain
 
// Print selected chain
 
always @ (posedge P_TCK)
 
always @ (posedge P_TCK)
 
begin
 
begin
 
  if(dbg_tb.dbgTAP1.CHAIN_SELECTSelected & dbg_tb.dbgTAP1.UpdateDR_q)
 
  if(dbg_tb.i_tap_top.CHAIN_SELECTSelected & dbg_tb.i_tap_top.UpdateDR_q)
 
    case(dbg_tb.dbgTAP1.Chain[`CHAIN_ID_LENGTH-1:0])
 
    case(dbg_tb.i_tap_top.i_dbg_top.Chain[`CHAIN_ID_LENGTH-1:0])
 
      `GLOBAL_BS_CHAIN      : $write("\nChain GLOBAL_BS_CHAIN");
 
      `GLOBAL_BS_CHAIN      : $write("\nChain GLOBAL_BS_CHAIN");
 
      `RISC_DEBUG_CHAIN     : $write("\nChain RISC_DEBUG_CHAIN");
 
      `RISC_DEBUG_CHAIN     : $write("\nChain RISC_DEBUG_CHAIN");
 
      `RISC_TEST_CHAIN      : $write("\nChain RISC_TEST_CHAIN");
 
      `RISC_TEST_CHAIN      : $write("\nChain RISC_TEST_CHAIN");
 
      `TRACE_TEST_CHAIN     : $write("\nChain TRACE_TEST_CHAIN");
 
      `TRACE_TEST_CHAIN     : $write("\nChain TRACE_TEST_CHAIN");
 
      `REGISTER_SCAN_CHAIN  : $write("\nChain REGISTER_SCAN_CHAIN");
 
      `REGISTER_SCAN_CHAIN  : $write("\nChain REGISTER_SCAN_CHAIN");
Line 768... Line 782... 
 
 
 
 
 
 
 
 
// print RISC registers read/write
 
// print RISC registers read/write
 
always @ (posedge Mclk)
 
always @ (posedge Mclk)
 
begin
 
begin
 
  if(dbg_tb.dbgTAP1.RISCAccess & ~dbg_tb.dbgTAP1.RISCAccess_q & dbg_tb.dbgTAP1.RW)
 
  if(dbg_tb.i_tap_top.i_dbg_top.RISCAccess & ~dbg_tb.i_tap_top.i_dbg_top.RISCAccess_q & dbg_tb.i_tap_top.i_dbg_top.RW)
 
    $write("\n\t\tWrite to RISC Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[31:0], dbg_tb.dbgTAP1.DataOut[31:0]);
 
    $write("\n\t\tWrite to RISC Register (addr=0x%h, data=0x%h)", dbg_tb.i_tap_top.i_dbg_top.ADDR[31:0], dbg_tb.i_tap_top.i_dbg_top.DataOut[31:0]);
 
  else
 
  else
 
  if(dbg_tb.dbgTAP1.RISCAccess_q & ~dbg_tb.dbgTAP1.RISCAccess_q2 & ~dbg_tb.dbgTAP1.RW)
 
  if(dbg_tb.i_tap_top.i_dbg_top.RISCAccess_q & ~dbg_tb.i_tap_top.i_dbg_top.RISCAccess_q2 & ~dbg_tb.i_tap_top.i_dbg_top.RW)
 
    $write("\n\t\tRead from RISC Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[31:0], dbg_tb.dbgTAP1.risc_data_i[31:0]);
 
    $write("\n\t\tRead from RISC Register (addr=0x%h, data=0x%h)", dbg_tb.i_tap_top.i_dbg_top.ADDR[31:0], dbg_tb.i_tap_top.i_dbg_top.risc_data_i[31:0]);
 
end
 
end
 
 
 
 
 
 
 
 
 
// print registers read/write
 
// print registers read/write
 
always @ (posedge Mclk)
 
always @ (posedge Mclk)
 
begin
 
begin
 
  if(dbg_tb.dbgTAP1.RegAccess_q & ~dbg_tb.dbgTAP1.RegAccess_q2)
 
  if(dbg_tb.i_tap_top.i_dbg_top.RegAccess_q & ~dbg_tb.i_tap_top.i_dbg_top.RegAccess_q2)
 
    begin
 
    begin
 
      if(dbg_tb.dbgTAP1.RW)
 
      if(dbg_tb.i_tap_top.i_dbg_top.RW)
 
        $write("\n\t\tWrite to Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[4:0], dbg_tb.dbgTAP1.DataOut[31:0]);
 
        $write("\n\t\tWrite to Register (addr=0x%h, data=0x%h)", dbg_tb.i_tap_top.i_dbg_top.ADDR[4:0], dbg_tb.i_tap_top.i_dbg_top.DataOut[31:0]);
 
      else
 
      else
 
        $write("\n\t\tRead from Register (addr=0x%h, data=0x%h). This data will be shifted out on next read request.", dbg_tb.dbgTAP1.ADDR[4:0], dbg_tb.dbgTAP1.RegDataIn[31:0]);
 
        $write("\n\t\tRead from Register (addr=0x%h, data=0x%h). This data will be shifted out on next read request.", dbg_tb.i_tap_top.i_dbg_top.ADDR[4:0], dbg_tb.i_tap_top.i_dbg_top.RegDataIn[31:0]);
 
    end
 
    end
 
end
 
end
 
 
 
 
 
 
 
 
 
// print CRC error
 
// print CRC error
 
`ifdef TRACE_ENABLED
 
`ifdef TRACE_ENABLED
 
  wire CRCErrorReport = ~(dbg_tb.dbgTAP1.CrcMatch & (dbg_tb.dbgTAP1.CHAIN_SELECTSelected | dbg_tb.dbgTAP1.DEBUGSelected & dbg_tb.dbgTAP1.RegisterScanChain | dbg_tb.dbgTAP1.DEBUGSelected & dbg_tb.dbgTAP1.RiscDebugScanChain | dbg_tb.dbgTAP1.DEBUGSelected & dbg_tb.dbgTAP1.TraceTestScanChain | dbg_tb.dbgTAP1.DEBUGSelected & dbg_tb.dbgTAP1.WishboneScanChain));
 
  wire CRCErrorReport = ~(dbg_tb.i_tap_top.i_dbg_top.CrcMatch & (dbg_tb.i_tap_top.CHAIN_SELECTSelected | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.RegisterScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.RiscDebugScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.TraceTestScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.WishboneScanChain));
 
`else  // TRACE_ENABLED not enabled
 
`else  // TRACE_ENABLED not enabled
 
  wire CRCErrorReport = ~(dbg_tb.dbgTAP1.CrcMatch & (dbg_tb.dbgTAP1.CHAIN_SELECTSelected | dbg_tb.dbgTAP1.DEBUGSelected & dbg_tb.dbgTAP1.RegisterScanChain | dbg_tb.dbgTAP1.DEBUGSelected & dbg_tb.dbgTAP1.RiscDebugScanChain | dbg_tb.dbgTAP1.DEBUGSelected & dbg_tb.dbgTAP1.WishboneScanChain));
 
  wire CRCErrorReport = ~(dbg_tb.i_tap_top.i_dbg_top.CrcMatch & (dbg_tb.i_tap_top.CHAIN_SELECTSelected | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.RegisterScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.RiscDebugScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.WishboneScanChain));
 
`endif
 
`endif
 
 
 
 
 
always @ (posedge P_TCK)
 
always @ (posedge P_TCK)
 
begin
 
begin
 
  if(dbg_tb.dbgTAP1.UpdateDR & ~dbg_tb.dbgTAP1.IDCODESelected)
 
  if(dbg_tb.i_tap_top.UpdateDR & ~dbg_tb.i_tap_top.IDCODESelected)
 
    begin
 
    begin
 
      if(dbg_tb.dbgTAP1.CHAIN_SELECTSelected)
 
      if(dbg_tb.i_tap_top.CHAIN_SELECTSelected)
 
        $write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.dbgTAP1.JTAG_DR_IN[11:4], dbg_tb.dbgTAP1.CalculatedCrcOut[`CRC_LENGTH-1:0]);
 
        $write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_tap_top.i_dbg_top.JTAG_DR_IN[11:4], dbg_tb.i_tap_top.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
 
      else
 
      else
 
      if(dbg_tb.dbgTAP1.RegisterScanChain & ~dbg_tb.dbgTAP1.CHAIN_SELECTSelected)
 
      if(dbg_tb.i_tap_top.RegisterScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
 
        $write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.dbgTAP1.JTAG_DR_IN[45:38], dbg_tb.dbgTAP1.CalculatedCrcOut[`CRC_LENGTH-1:0]);
 
        $write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_tap_top.i_dbg_top.JTAG_DR_IN[45:38], dbg_tb.i_tap_top.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
 
      else
 
      else
 
      if(dbg_tb.dbgTAP1.RiscDebugScanChain & ~dbg_tb.dbgTAP1.CHAIN_SELECTSelected)
 
      if(dbg_tb.i_tap_top.RiscDebugScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
 
        $write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.dbgTAP1.JTAG_DR_IN[72:65], dbg_tb.dbgTAP1.CalculatedCrcOut[`CRC_LENGTH-1:0]);
 
        $write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_tap_top.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_tap_top.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
 
      if(dbg_tb.dbgTAP1.WishboneScanChain & ~dbg_tb.dbgTAP1.CHAIN_SELECTSelected)
 
      if(dbg_tb.i_tap_top.WishboneScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
 
        $write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.dbgTAP1.JTAG_DR_IN[72:65], dbg_tb.dbgTAP1.CalculatedCrcOut[`CRC_LENGTH-1:0]);
 
        $write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_tap_top.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_tap_top.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
 
 
 
 
 
      if(CRCErrorReport)
 
      if(CRCErrorReport)
 
        begin
 
        begin
 
          $write("\n\t\t\t\tCrc Error when receiving data (read or write) !!!  CrcIn should be: 0x%h\n", dbg_tb.dbgTAP1.CalculatedCrcIn);
 
          $write("\n\t\t\t\tCrc Error when receiving data (read or write) !!!  CrcIn should be: 0x%h\n", dbg_tb.i_tap_top.i_dbg_top.CalculatedCrcIn);
 
          #1000 $stop;
 
          #1000 $stop;
 
        end
 
        end
 
    end
 
    end
 
end
 
end
 
 
 
 
 
 
 
 
 
// Print shifted IDCode
 
// Print shifted IDCode
 
reg [31:0] TempData;
 
reg [31:0] TempData;
 
always @ (posedge P_TCK)
 
always @ (posedge P_TCK)
 
begin
 
begin
 
  if(dbg_tb.dbgTAP1.IDCODESelected)
 
  if(dbg_tb.i_tap_top.IDCODESelected)
 
    begin
 
    begin
 
      if(dbg_tb.dbgTAP1.ShiftDR)
 
      if(dbg_tb.i_tap_top.ShiftDR)
 
        TempData[31:0]<=#Tp {dbg_tb.dbgTAP1.TDOData, TempData[31:1]};
 
        TempData[31:0]<=#Tp {dbg_tb.i_tap_top.TDOData, TempData[31:1]};
 
      else
 
      else
 
      if(dbg_tb.dbgTAP1.UpdateDR)
 
      if(dbg_tb.i_tap_top.UpdateDR)
 
        $write("\n\t\tIDCode = 0x%h", TempData[31:0]);
 
        $write("\n\t\tIDCode = 0x%h", TempData[31:0]);
 
    end
 
    end
 
end
 
end
 
 
 
 
 
 
 
 
 
// Print data from the trace buffer
 
// Print data from the trace buffer
 
reg [47:0] TraceData;
 
reg [47:0] TraceData;
 
always @ (posedge P_TCK)
 
always @ (posedge P_TCK)
 
begin
 
begin
 
  if(dbg_tb.dbgTAP1.DEBUGSelected & (dbg_tb.dbgTAP1.Chain==`TRACE_TEST_CHAIN))
 
  if(dbg_tb.i_tap_top.DEBUGSelected & (dbg_tb.i_tap_top.i_dbg_top.Chain==`TRACE_TEST_CHAIN))
 
    begin
 
    begin
 
      if(dbg_tb.dbgTAP1.ShiftDR)
 
      if(dbg_tb.i_tap_top.ShiftDR)
 
        TraceData[47:0]<=#Tp {dbg_tb.dbgTAP1.TDOData, TraceData[47:1]};
 
        TraceData[47:0]<=#Tp {dbg_tb.i_tap_top.TDOData, TraceData[47:1]};
 
      else
 
      else
 
      if(dbg_tb.dbgTAP1.UpdateDR)
 
      if(dbg_tb.i_tap_top.UpdateDR)
 
        $write("\n\t\TraceData = 0x%h + Crc = 0x%h", TraceData[39:0], TraceData[47:40]);
 
        $write("\n\t\TraceData = 0x%h + Crc = 0x%h", TraceData[39:0], TraceData[47:40]);
 
    end
 
    end
 
end
 
end
 
 
 
 
 
 
 
 

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