Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.13 2003/08/28 13:54:33 simons
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|
// Three more chains added for cpu debug access.
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//
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// Revision 1.12 2002/05/07 14:44:52 mohor
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// Revision 1.12 2002/05/07 14:44:52 mohor
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// mon_cntl_o signals that controls monitor mux added.
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// mon_cntl_o signals that controls monitor mux added.
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//
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//
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// Revision 1.11 2002/03/12 14:32:26 mohor
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// Revision 1.11 2002/03/12 14:32:26 mohor
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// Few outputs for boundary scan chain added.
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// Few outputs for boundary scan chain added.
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Line 114... |
Line 117... |
reg [10:0] Wp;
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reg [10:0] Wp;
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reg Bp;
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reg Bp;
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reg [3:0] LsStatus;
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reg [3:0] LsStatus;
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reg [1:0] IStatus;
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reg [1:0] IStatus;
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reg BS_CHAIN_I;
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reg BS_CHAIN_I;
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reg MBIST_I;
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|
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wire P_TDO;
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wire P_TDO;
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wire [31:0] ADDR_RISC;
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wire [31:0] ADDR_CPU;
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wire [31:0] DATAIN_RISC; // DATAIN_RISC is connect to DATAOUT
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wire [31:0] DATAIN_CPU; // DATAIN_CPU is connect to DATAOUT
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|
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wire [31:0] DATAOUT_RISC; // DATAOUT_RISC is connect to DATAIN
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wire [31:0] DATAOUT_CPU; // DATAOUT_CPU is connect to DATAIN
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|
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wire [`OPSELECTWIDTH-1:0] OpSelect;
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wire [`OPSELECTWIDTH-1:0] OpSelect;
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|
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wire [31:0] wb_adr_i;
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wire [31:0] wb_adr_i;
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wire [31:0] wb_dat_i;
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wire [31:0] wb_dat_i;
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Line 139... |
Line 143... |
wire ShiftDR;
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wire ShiftDR;
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wire Exit1DR;
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wire Exit1DR;
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wire UpdateDR;
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wire UpdateDR;
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wire UpdateDR_q;
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wire UpdateDR_q;
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wire CaptureDR;
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wire CaptureDR;
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wire SelectDRScan;
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wire IDCODESelected;
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wire IDCODESelected;
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wire CHAIN_SELECTSelected;
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wire CHAIN_SELECTSelected;
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wire DEBUGSelected;
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wire DEBUGSelected;
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wire TDOData_dbg;
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wire TDOData_dbg;
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wire BypassRegister;
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wire BypassRegister;
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wire EXTESTSelected;
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wire EXTESTSelected;
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wire MBISTSelected;
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wire [3:0] mon_cntl_o;
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wire [3:0] mon_cntl_o;
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wire CpuDebugScanChain0;
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wire CpuDebugScanChain1;
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wire CpuDebugScanChain2;
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wire CpuDebugScanChain3;
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|
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// Connecting TAP module
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// Connecting TAP module
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tap_top i_tap_top
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tap_top i_tap_top
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(.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI),
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(.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI),
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.tdo_pad_o(P_TDO), .tdo_padoe_o(tdo_padoe_o),
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.tdo_pad_o(P_TDO), .tdo_padoe_o(tdo_padoe_o),
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// TAP states
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// TAP states
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.ShiftDR(ShiftDR), .Exit1DR(Exit1DR), .UpdateDR(UpdateDR), .UpdateDR_q(UpdateDR_q),
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.ShiftDR(ShiftDR), .Exit1DR(Exit1DR), .UpdateDR(UpdateDR), .UpdateDR_q(UpdateDR_q),
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.CaptureDR(CaptureDR),
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.CaptureDR(CaptureDR), .SelectDRScan(SelectDRScan),
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|
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// Instructions
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// Instructions
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.IDCODESelected(IDCODESelected), .CHAIN_SELECTSelected(CHAIN_SELECTSelected),
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.IDCODESelected(IDCODESelected), .CHAIN_SELECTSelected(CHAIN_SELECTSelected),
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.DEBUGSelected(DEBUGSelected), .EXTESTSelected(EXTESTSelected),
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.DEBUGSelected(DEBUGSelected), .EXTESTSelected(EXTESTSelected),
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.MBISTSelected(MBISTSelected),
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|
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// TDO from dbg module
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// TDO from dbg module
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.TDOData_dbg(TDOData_dbg), .BypassRegister(BypassRegister),
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.TDOData_dbg(TDOData_dbg), .BypassRegister(BypassRegister),
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// Boundary Scan Chain
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// Boundary Scan Chain
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.bs_chain_i(BS_CHAIN_I)
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.bs_chain_i(BS_CHAIN_I),
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// From Mbist Chain
|
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.mbist_so_i(MBIST_I),
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|
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// Selected chains
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.RegisterScanChain(RegisterScanChain),
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.CpuDebugScanChain0(CpuDebugScanChain0),
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.CpuDebugScanChain1(CpuDebugScanChain1),
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.CpuDebugScanChain2(CpuDebugScanChain2),
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.CpuDebugScanChain3(CpuDebugScanChain3),
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.WishboneScanChain(WishboneScanChain)
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|
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);
|
);
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|
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|
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dbg_top i_dbg_top
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dbg_top i_dbg_top
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(
|
(
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.risc_clk_i(Mclk), .risc_addr_o(ADDR_RISC), .risc_data_i(DATAOUT_RISC),
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.cpu_clk_i(Mclk), .cpu_addr_o(ADDR_CPU), .cpu_data_i(DATAOUT_CPU),
|
.risc_data_o(DATAIN_RISC), .wp_i(Wp), .bp_i(Bp), .opselect_o(OpSelect),
|
.cpu_data_o(DATAIN_CPU), .wp_i(Wp), .bp_i(Bp), .opselect_o(OpSelect),
|
.lsstatus_i(LsStatus), .istatus_i(IStatus), .risc_stall_o(), .reset_o(),
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.lsstatus_i(LsStatus), .istatus_i(IStatus), .cpu_stall_o(),
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.cpu_stall_all_o(), .cpu_sel_o(), .reset_o(),
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|
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.wb_rst_i(wb_rst_i), .wb_clk_i(Mclk),
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.wb_rst_i(wb_rst_i), .wb_clk_i(Mclk),
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|
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.wb_adr_o(wb_adr_i), .wb_dat_o(wb_dat_i), .wb_dat_i(wb_dat_o),
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.wb_adr_o(wb_adr_i), .wb_dat_o(wb_dat_i), .wb_dat_i(wb_dat_o),
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.wb_cyc_o(wb_cyc_i), .wb_stb_o(wb_stb_i), .wb_sel_o(wb_sel_i),
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.wb_cyc_o(wb_cyc_i), .wb_stb_o(wb_stb_i), .wb_sel_o(wb_sel_i),
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.wb_we_o(wb_we_i), .wb_ack_i(wb_ack_o), .wb_cab_o(wb_cab_i),
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.wb_we_o(wb_we_i), .wb_ack_i(wb_ack_o), .wb_cab_o(wb_cab_i),
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.wb_err_i(wb_err_o),
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.wb_err_i(wb_err_o),
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// TAP states
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// TAP states
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.ShiftDR(ShiftDR), .Exit1DR(Exit1DR), .UpdateDR(UpdateDR), .UpdateDR_q(UpdateDR_q),
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.ShiftDR(ShiftDR), .Exit1DR(Exit1DR), .UpdateDR(UpdateDR), .UpdateDR_q(UpdateDR_q),
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.SelectDRScan(SelectDRScan),
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// Instructions
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// Instructions
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.IDCODESelected(IDCODESelected), .CHAIN_SELECTSelected(CHAIN_SELECTSelected),
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.IDCODESelected(IDCODESelected), .CHAIN_SELECTSelected(CHAIN_SELECTSelected),
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.DEBUGSelected(DEBUGSelected),
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.DEBUGSelected(DEBUGSelected),
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|
Line 194... |
Line 221... |
.trst_in(P_TRST), .tck(P_TCK), .tdi(P_TDI), .TDOData(TDOData_dbg),
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.trst_in(P_TRST), .tck(P_TCK), .tdi(P_TDI), .TDOData(TDOData_dbg),
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|
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.BypassRegister(BypassRegister),
|
.BypassRegister(BypassRegister),
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|
|
|
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.mon_cntl_o(mon_cntl_o)
|
.mon_cntl_o(mon_cntl_o),
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|
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|
// Selected chains
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.RegisterScanChain(RegisterScanChain),
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.CpuDebugScanChain0(CpuDebugScanChain0),
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.CpuDebugScanChain1(CpuDebugScanChain1),
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.CpuDebugScanChain2(CpuDebugScanChain2),
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.CpuDebugScanChain3(CpuDebugScanChain3),
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.WishboneScanChain(WishboneScanChain)
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|
|
);
|
);
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|
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reg TestEnabled;
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reg TestEnabled;
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Line 209... |
Line 244... |
TestEnabled<=#Tp 0;
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TestEnabled<=#Tp 0;
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P_TMS<=#Tp 'hz;
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P_TMS<=#Tp 'hz;
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P_TCK<=#Tp 'hz;
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P_TCK<=#Tp 'hz;
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P_TDI<=#Tp 'hz;
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P_TDI<=#Tp 'hz;
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BS_CHAIN_I = 0;
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BS_CHAIN_I = 0;
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MBIST_I = 0;
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Wp<=#Tp 0;
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Wp<=#Tp 0;
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Bp<=#Tp 0;
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Bp<=#Tp 0;
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LsStatus<=#Tp 0;
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LsStatus<=#Tp 0;
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IStatus<=#Tp 0;
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IStatus<=#Tp 0;
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Line 222... |
Line 258... |
wb_err_o<=#Tp 1'h0;
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wb_err_o<=#Tp 1'h0;
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wb_rst_i<=#Tp 0;
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wb_rst_i<=#Tp 0;
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P_TRST<=#Tp 1;
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#100 wb_rst_i<=#Tp 1;
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P_TRST<=#Tp 0;
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P_TRST<=#Tp 0;
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#100 wb_rst_i<=#Tp 0;
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#100 wb_rst_i<=#Tp 1;
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P_TRST<=#Tp 1;
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P_TRST<=#Tp 1;
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#100 wb_rst_i<=#Tp 0;
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P_TRST<=#Tp 0;
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#Tp TestEnabled<=#Tp 1;
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#Tp TestEnabled<=#Tp 1;
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end
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end
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// Generating master clock (RISC clock) 200 MHz
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// Generating master clock (cpu clock) 200 MHz
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initial
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initial
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begin
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begin
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Mclk<=#Tp 0;
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Mclk<=#Tp 0;
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#1 forever #`RISC_CLOCK Mclk<=~Mclk;
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#1 forever #`CPU_CLOCK Mclk<=~Mclk;
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end
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end
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// Generating random number for use in DATAOUT_RISC[31:0]
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// Generating random number for use in DATAOUT_CPU[31:0]
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reg [31:0] RandNumb;
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reg [31:0] RandNumb;
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always @ (posedge Mclk or posedge wb_rst_i)
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always @ (posedge Mclk or posedge wb_rst_i)
|
begin
|
begin
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if(wb_rst_i)
|
if(wb_rst_i)
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RandNumb[31:0]<=#Tp 0;
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RandNumb[31:0]<=#Tp 0;
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else
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else
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RandNumb[31:0]<=#Tp RandNumb[31:0] + 1;
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RandNumb[31:0]<=#Tp RandNumb[31:0] + 1;
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end
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end
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assign DATAOUT_RISC[31:0] = RandNumb[31:0];
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assign DATAOUT_CPU[31:0] = RandNumb[31:0];
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always @ (posedge TestEnabled)
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always @ (posedge TestEnabled)
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begin
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$display("//////////////////////////////////////////////////////////////////////////////////////");
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$display("// //");
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$display("// (%0t) dbg_tb starting //", $time);
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$display("// //");
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$display("//////////////////////////////////////////////////////////////////////////////////////");
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fork
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fork
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begin
|
begin
|
EnableWishboneSlave; // enabling WISHBONE slave
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EnableWishboneSlave; // enabling WISHBONE slave
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end
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end
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|
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begin
|
begin
|
ResetTAP;
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ResetTAP;
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GotoRunTestIdle;
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GotoRunTestIdle;
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// Testing read and write to WISHBONE
|
// Testing read and write to WISHBONE (WB and CPU chain are the same)
|
SetInstruction(`CHAIN_SELECT);
|
SetInstruction(`CHAIN_SELECT);
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ChainSelect(`WISHBONE_SCAN_CHAIN, 8'h36); // {chain, crc}
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ChainSelect(`WISHBONE_SCAN_CHAIN, 8'h36); // {chain, crc}
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SetInstruction(`DEBUG);
|
SetInstruction(`DEBUG);
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ReadRISCRegister(32'h87654321, 8'hfd); // {addr, crc} // Wishbone and RISC accesses are similar
|
WriteCPURegister(32'h18273645, 32'hbeefbeef, 8'haa); // {data, addr, crc}
|
WriteRISCRegister(32'h18273645, 32'hbeefbeef, 8'haa); // {data, addr, crc}
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ReadRISCRegister(32'h87654321, 8'hfd); // {addr, crc} // Wishbone and RISC accesses are similar
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ReadRISCRegister(32'h87654321, 8'hfd); // {addr, crc} // Wishbone and RISC accesses are similar
|
|
//
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|
|
|
// Testing read and write to RISC registers
|
#10000;
|
|
ReadCPURegister(32'h87654321, 8'hfd); // {addr, crc} // Wishbone and CPU accesses are similar
|
|
ReadCPURegister(32'h87654321, 8'hfd); // {addr, crc} // Wishbone and CPU accesses are similar
|
|
|
|
// Testing read and write to CPU0 registers
|
|
#10000;
|
SetInstruction(`CHAIN_SELECT);
|
SetInstruction(`CHAIN_SELECT);
|
ChainSelect(`RISC_DEBUG_CHAIN_2, 8'h38); // {chain, crc}
|
ChainSelect(`CPU_DEBUG_CHAIN_0, 8'h12); // {chain, crc}
|
SetInstruction(`DEBUG);
|
SetInstruction(`DEBUG);
|
|
WriteCPURegister(32'h11001100, 32'h00110011, 8'h86); // {data, addr, crc}
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|
|
ReadRISCRegister(32'h12345ead, 8'hbf); // {addr, crc}
|
ReadCPURegister(32'h11001100, 8'hdb); // {addr, crc}
|
WriteRISCRegister(32'h11223344, 32'h12345678, 8'haf); // {data, addr, crc}
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ReadCPURegister(32'h11001100, 8'hdb); // {addr, crc}
|
//
|
|
|
// Testing read and write to CPU1 registers
|
|
#10000;
|
|
SetInstruction(`CHAIN_SELECT);
|
|
ChainSelect(`CPU_DEBUG_CHAIN_1, 8'h2a); // {chain, crc}
|
|
SetInstruction(`DEBUG);
|
|
WriteCPURegister(32'h22002200, 32'h00220022, 8'h10); // {data, addr, crc}
|
|
|
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ReadCPURegister(32'h22002200, 8'hee); // {addr, crc}
|
|
ReadCPURegister(32'h22002200, 8'hee); // {addr, crc}
|
|
|
|
// Testing read and write to CPU2 registers
|
|
#10000;
|
|
SetInstruction(`CHAIN_SELECT);
|
|
ChainSelect(`CPU_DEBUG_CHAIN_2, 8'h38); // {chain, crc}
|
|
SetInstruction(`DEBUG);
|
|
WriteCPURegister(32'h33003300, 32'h00330033, 8'hf4); // {data, addr, crc}
|
|
|
|
ReadCPURegister(32'h33003300, 8'h35); // {addr, crc}
|
|
ReadCPURegister(32'h33003300, 8'h35); // {addr, crc}
|
|
|
|
// Testing read and write to CPU3 registers
|
|
#10000;
|
|
SetInstruction(`CHAIN_SELECT);
|
|
ChainSelect(`CPU_DEBUG_CHAIN_3, 8'h07); // {chain, crc}
|
|
SetInstruction(`DEBUG);
|
|
WriteCPURegister(32'h44004400, 32'h00440044, 8'h5b); // {data, addr, crc}
|
|
|
|
ReadCPURegister(32'h44004400, 8'h77); // {addr, crc}
|
|
ReadCPURegister(32'h44004400, 8'h77); // {addr, crc}
|
|
|
// Testing read and write to internal registers
|
// Testing read and write to internal registers
|
|
#10000;
|
SetInstruction(`IDCODE);
|
SetInstruction(`IDCODE);
|
ReadIDCode; // muten
|
ReadIDCode;
|
|
|
SetInstruction(`CHAIN_SELECT);
|
SetInstruction(`CHAIN_SELECT);
|
ChainSelect(`REGISTER_SCAN_CHAIN, 8'h0e); // {chain, crc}
|
ChainSelect(`REGISTER_SCAN_CHAIN, 8'h0e); // {chain, crc}
|
SetInstruction(`DEBUG);
|
SetInstruction(`DEBUG);
|
|
|
|
|
//
|
|
// Testing internal registers
|
// Testing internal registers
|
ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
|
WriteRegister(32'h00000001, `CPUOP_ADR, 8'h4a); // {data, addr, crc}
|
ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
|
WriteRegister(32'h00000002, `CPUOP_ADR, 8'he0); // {data, addr, crc}
|
ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
|
WriteRegister(32'h00000004, `CPUOP_ADR, 8'hb5); // {data, addr, crc}
|
ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
|
WriteRegister(32'h00000000, `CPUSEL_ADR, 8'h1f); // {data, addr, crc}
|
ReadRegister(`RECSEL_ADR, 8'hc4); // {addr, crc}
|
WriteRegister(32'h00000001, `CPUSEL_ADR, 8'h2e); // {data, addr, crc}
|
ReadRegister(`MON_CNTL_ADR, 8'ha0); // {addr, crc}
|
WriteRegister(32'h00000002, `CPUSEL_ADR, 8'h84); // {data, addr, crc}
|
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
|
|
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
|
ReadRegister(`CPUOP_ADR, 8'h19); // {addr, crc}
|
|
ReadRegister(`CPUOP_ADR, 8'h19); // {addr, crc}
|
WriteRegister(32'h00000001, `MODER_ADR, 8'h53); // {data, addr, crc}
|
ReadRegister(`CPUSEL_ADR, 8'h7d); // {addr, crc}
|
WriteRegister(32'h00000020, `TSEL_ADR, 8'h5e); // {data, addr, crc}
|
ReadRegister(`CPUSEL_ADR, 8'h7d); // {addr, crc}
|
WriteRegister(32'h00000300, `QSEL_ADR, 8'hdd); // {data, addr, crc}
|
|
WriteRegister(32'h00004000, `SSEL_ADR, 8'he2); // {data, addr, crc}
|
//ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
|
WriteRegister(32'h0000dead, `RECSEL_ADR, 8'hfb); // {data, addr, crc}
|
//ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
|
WriteRegister(32'h0000000d, `MON_CNTL_ADR, 8'h5a); // {data, addr, crc}
|
//ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
|
|
//ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
|
ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
|
//ReadRegister(`RECSEL_ADR, 8'hc4); // {addr, crc}
|
ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
|
//ReadRegister(`MON_CNTL_ADR, 8'ha0); // {addr, crc}
|
ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
|
//ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
|
ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
|
//ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
|
ReadRegister(`RECSEL_ADR, 8'hc4); // {addr, crc}
|
|
ReadRegister(`MON_CNTL_ADR, 8'ha0); // {addr, crc}
|
//WriteRegister(32'h00000001, `MODER_ADR, 8'h53); // {data, addr, crc}
|
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
|
//WriteRegister(32'h00000020, `TSEL_ADR, 8'h5e); // {data, addr, crc}
|
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
|
//WriteRegister(32'h00000300, `QSEL_ADR, 8'hdd); // {data, addr, crc}
|
//
|
//WriteRegister(32'h00004000, `SSEL_ADR, 8'he2); // {data, addr, crc}
|
|
//WriteRegister(32'h0000dead, `RECSEL_ADR, 8'hfb); // {data, addr, crc}
|
|
//WriteRegister(32'h0000000d, `MON_CNTL_ADR, 8'h5a); // {data, addr, crc}
|
|
|
|
|
// testing trigger and qualifier
|
// testing trigger and qualifier
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
|
|
|
|
|
|
|
|
|
|
// Anything starts trigger and qualifier
|
// Anything starts trigger and qualifier
|
#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
|
#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
|
#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
|
#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
|
#1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
|
#1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
|
#100 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
|
#100 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
|
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
|
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
|
// End: Anything starts trigger and qualifier //
|
// End: Anything starts trigger and qualifier //
|
|
|
|
|
/* Anything starts trigger, breakpoint starts qualifier
|
/* Anything starts trigger, breakpoint starts qualifier
|
// Uncomment this part when you want to test it.
|
// Uncomment this part when you want to test it.
|
#1000 WriteRegister(`QUALIFOP_OR | `BPQUALIFVALID | `BPQUALIF, `QSEL_ADR, 8'had); // Any qualifier
|
#1000 WriteRegister(`QUALIFOP_OR | `BPQUALIFVALID | `BPQUALIF, `QSEL_ADR, 8'had); // Any qualifier
|
#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
|
#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
|
#1000 WriteRegister(32'h0000000c, `RECSEL_ADR, 8'h0f); // Two samples are selected for recording (RECSDATA and RECLDATA)
|
#1000 WriteRegister(32'h0000000c, `RECSEL_ADR, 8'h0f); // Two samples are selected for recording (RECSDATA and RECLDATA)
|
Line 350... |
Line 421... |
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
|
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
|
wait(dbg_tb.i_dbg_top.TraceEnable)
|
wait(dbg_tb.i_dbg_top.TraceEnable)
|
@ (posedge Mclk);
|
@ (posedge Mclk);
|
#1 Bp = 1; // Set breakpoint
|
#1 Bp = 1; // Set breakpoint
|
repeat(8) @(posedge Mclk);
|
repeat(8) @(posedge Mclk);
|
wait(dbg_tb.i_dbg_top.dbgTrace1.RiscStall)
|
wait(dbg_tb.i_dbg_top.dbgTrace1.CpuStall)
|
#1 Bp = 0; // Clear breakpoint
|
#1 Bp = 0; // Clear breakpoint
|
// End: Anything starts trigger, breakpoint starts qualifier */
|
// End: Anything starts trigger, breakpoint starts qualifier */
|
|
|
|
|
/* Anything starts qualifier, breakpoint starts trigger
|
/* Anything starts qualifier, breakpoint starts trigger
|
// Uncomment this part when you want to test it.
|
// Uncomment this part when you want to test it.
|
#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
|
#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
|
#1000 WriteRegister(`LSSTRIG_0 | `LSSTRIG_2 | `LSSTRIGVALID | `WPTRIG_4 | `WPTRIGVALID | `TRIGOP_AND, `TSEL_ADR, 8'had); // Trigger is AND of Watchpoint4 and LSSTRIG[0] and LSSTRIG[2]
|
#1000 WriteRegister(`LSSTRIG_0 | `LSSTRIG_2 | `LSSTRIGVALID | `WPTRIG_4 | `WPTRIGVALID | `TRIGOP_AND, `TSEL_ADR, 8'had); // Trigger is AND of Watchpoint4 and LSSTRIG[0] and LSSTRIG[2]
|
#1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
|
#1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
|
Line 371... |
Line 441... |
@ (posedge Mclk)
|
@ (posedge Mclk)
|
Wp[4] = 0; // Clear watchpoint[4]
|
Wp[4] = 0; // Clear watchpoint[4]
|
LsStatus = 4'h0; // LsStatus[0] and LsStatus[2] are cleared
|
LsStatus = 4'h0; // LsStatus[0] and LsStatus[2] are cleared
|
// End: Anything starts trigger and qualifier */
|
// End: Anything starts trigger and qualifier */
|
|
|
|
|
|
|
|
|
|
|
|
|
// Reading data from the trace buffer
|
// Reading data from the trace buffer
|
SetInstruction(`CHAIN_SELECT);
|
SetInstruction(`CHAIN_SELECT);
|
ChainSelect(`TRACE_TEST_CHAIN, 8'h24); // {chain, crc}
|
ChainSelect(`TRACE_TEST_CHAIN, 8'h24); // {chain, crc}
|
SetInstruction(`DEBUG);
|
SetInstruction(`DEBUG);
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
Line 392... |
Line 457... |
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
ReadTraceBuffer;
|
|
|
|
|
`endif // TRACE_ENABLED
|
`endif // TRACE_ENABLED
|
|
|
|
|
|
|
|
|
#5000 GenClk(1); // One extra TCLK for debugging purposes
|
#5000 GenClk(1); // One extra TCLK for debugging purposes
|
#1000 $stop;
|
#1000 $stop;
|
|
|
end
|
end
|
join
|
join
|
|
end
|
|
|
// Generation of the TCLK signal
|
// Generation of the TCLK signal
|
task GenClk;
|
task GenClk;
|
input [7:0] Number;
|
input [7:0] Number;
|
integer i;
|
integer i;
|
Line 423... |
Line 486... |
|
|
|
|
// TAP reset
|
// TAP reset
|
task ResetTAP;
|
task ResetTAP;
|
begin
|
begin
|
|
$display("(%0t) Task ResetTAP", $time);
|
P_TMS<=#Tp 1;
|
P_TMS<=#Tp 1;
|
GenClk(7);
|
GenClk(7);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
// Goes to RunTestIdle state
|
// Goes to RunTestIdle state
|
task GotoRunTestIdle;
|
task GotoRunTestIdle;
|
begin
|
begin
|
|
$display("(%0t) Task GotoRunTestIdle", $time);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(1);
|
GenClk(1);
|
end
|
end
|
endtask
|
endtask
|
|
|
Line 444... |
Line 509... |
task SetInstruction;
|
task SetInstruction;
|
input [3:0] Instr;
|
input [3:0] Instr;
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
|
$display("(%0t) Task SetInstruction", $time);
|
P_TMS<=#Tp 1;
|
P_TMS<=#Tp 1;
|
GenClk(2);
|
GenClk(2);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(2); // we are in shiftIR
|
GenClk(2); // we are in shiftIR
|
|
|
Line 473... |
Line 539... |
input [3:0] Data;
|
input [3:0] Data;
|
input [7:0] Crc;
|
input [7:0] Crc;
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
|
$display("(%0t) Task ChainSelect", $time);
|
P_TMS<=#Tp 1;
|
P_TMS<=#Tp 1;
|
GenClk(1);
|
GenClk(1);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(2); // we are in shiftDR
|
GenClk(2); // we are in shiftDR
|
|
|
Line 506... |
Line 573... |
|
|
|
|
// Reads the ID code
|
// Reads the ID code
|
task ReadIDCode;
|
task ReadIDCode;
|
begin
|
begin
|
|
$display("(%0t) Task ReadIDCode", $time);
|
P_TMS<=#Tp 1;
|
P_TMS<=#Tp 1;
|
GenClk(1);
|
GenClk(1);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(2); // we are in shiftDR
|
GenClk(2); // we are in shiftDR
|
|
|
Line 528... |
Line 596... |
|
|
|
|
// Reads sample from the Trace Buffer
|
// Reads sample from the Trace Buffer
|
task ReadTraceBuffer;
|
task ReadTraceBuffer;
|
begin
|
begin
|
|
$display("(%0t) Task ReadTraceBuffer", $time);
|
P_TMS<=#Tp 1;
|
P_TMS<=#Tp 1;
|
GenClk(1);
|
GenClk(1);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(2); // we are in shiftDR
|
GenClk(2); // we are in shiftDR
|
|
|
Line 545... |
Line 614... |
GenClk(1); // we are in RunTestIdle
|
GenClk(1); // we are in RunTestIdle
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
// Reads the RISC register and latches the data so it is ready for reading
|
// Reads the CPU register and latches the data so it is ready for reading
|
task ReadRISCRegister;
|
task ReadCPURegister;
|
input [31:0] Address;
|
input [31:0] Address;
|
input [7:0] Crc;
|
input [7:0] Crc;
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
|
$display("(%0t) Task ReadCPURegister", $time);
|
P_TMS<=#Tp 1;
|
P_TMS<=#Tp 1;
|
GenClk(1);
|
GenClk(1);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(2); // we are in shiftDR
|
GenClk(2); // we are in shiftDR
|
|
|
Line 592... |
Line 662... |
GenClk(1); // we are in RunTestIdle
|
GenClk(1); // we are in RunTestIdle
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
// Write the RISC register
|
// Write the CPU register
|
task WriteRISCRegister;
|
task WriteCPURegister;
|
input [31:0] Data;
|
input [31:0] Data;
|
input [31:0] Address;
|
input [31:0] Address;
|
input [`CRC_LENGTH-1:0] Crc;
|
input [`CRC_LENGTH-1:0] Crc;
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
|
$display("(%0t) Task WriteCPURegister", $time);
|
P_TMS<=#Tp 1;
|
P_TMS<=#Tp 1;
|
GenClk(1);
|
GenClk(1);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(2); // we are in shiftDR
|
GenClk(2); // we are in shiftDR
|
|
|
Line 649... |
Line 720... |
input [4:0] Address;
|
input [4:0] Address;
|
input [7:0] Crc;
|
input [7:0] Crc;
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
|
$display("(%0t) Task ReadRegister", $time);
|
P_TMS<=#Tp 1;
|
P_TMS<=#Tp 1;
|
GenClk(1);
|
GenClk(1);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(2); // we are in shiftDR
|
GenClk(2); // we are in shiftDR
|
|
|
Line 698... |
Line 770... |
input [4:0] Address;
|
input [4:0] Address;
|
input [`CRC_LENGTH-1:0] Crc;
|
input [`CRC_LENGTH-1:0] Crc;
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
|
$display("(%0t) Task WriteRegister", $time);
|
P_TMS<=#Tp 1;
|
P_TMS<=#Tp 1;
|
GenClk(1);
|
GenClk(1);
|
P_TMS<=#Tp 0;
|
P_TMS<=#Tp 0;
|
GenClk(2); // we are in shiftDR
|
GenClk(2); // we are in shiftDR
|
|
|
Line 743... |
Line 816... |
endtask
|
endtask
|
|
|
|
|
task EnableWishboneSlave;
|
task EnableWishboneSlave;
|
begin
|
begin
|
|
$display("(%0t) Task EnableWishboneSlave", $time);
|
while(1)
|
while(1)
|
begin
|
begin
|
|
@ (posedge Mclk);
|
if(wb_stb_i & wb_cyc_i) // WB access
|
if(wb_stb_i & wb_cyc_i) // WB access
|
// wait (wb_stb_i & wb_cyc_i) // WB access
|
// wait (wb_stb_i & wb_cyc_i) // WB access
|
begin
|
begin
|
@ (posedge Mclk);
|
@ (posedge Mclk);
|
@ (posedge Mclk);
|
@ (posedge Mclk);
|
@ (posedge Mclk);
|
@ (posedge Mclk);
|
#1 wb_ack_o = 1;
|
#1 wb_ack_o = 1;
|
if(~wb_we_i) // read
|
if(~wb_we_i) // read
|
wb_dat_o = 32'hbeefdead;
|
wb_dat_o = 32'hbeefdead;
|
|
wb_dat_o = {wb_adr_i[3:0], wb_adr_i[7:4], wb_adr_i[11:8], wb_adr_i[15:12],
|
|
wb_adr_i[19:16], wb_adr_i[23:20], wb_adr_i[27:24], wb_adr_i[31:28]};
|
if(wb_we_i & wb_stb_i & wb_cyc_i) // write
|
if(wb_we_i & wb_stb_i & wb_cyc_i) // write
|
$display("\nWISHBONE write Data=%0h, Addr=%0h", wb_dat_i, wb_adr_i);
|
$display("\nWISHBONE write Data=%0h, Addr=%0h", wb_dat_i, wb_adr_i);
|
if(~wb_we_i & wb_stb_i & wb_cyc_i) // read
|
if(~wb_we_i & wb_stb_i & wb_cyc_i) // read
|
$display("\nWISHBONE read Data=%0h, Addr=%0h", wb_dat_o, wb_adr_i);
|
$display("\nWISHBONE read Data=%0h, Addr=%0h", wb_dat_o, wb_adr_i);
|
end
|
end
|
Line 806... |
Line 883... |
|
|
always @ (posedge P_TCK)
|
always @ (posedge P_TCK)
|
begin
|
begin
|
if(UpdateIR_q)
|
if(UpdateIR_q)
|
case(dbg_tb.i_tap_top.LatchedJTAG_IR[`IR_LENGTH-1:0])
|
case(dbg_tb.i_tap_top.LatchedJTAG_IR[`IR_LENGTH-1:0])
|
`EXTEST : $write("\n\tInstruction EXTEST");
|
`EXTEST : $write("\tInstruction EXTEST entered");
|
`SAMPLE_PRELOAD : $write("\n\tInstruction SAMPLE_PRELOAD");
|
`SAMPLE_PRELOAD : $write("\tInstruction SAMPLE_PRELOAD entered");
|
`IDCODE : $write("\n\tInstruction IDCODE");
|
`IDCODE : $write("\tInstruction IDCODE entered");
|
`CHAIN_SELECT : $write("\n\tInstruction CHAIN_SELECT");
|
`CHAIN_SELECT : $write("\tInstruction CHAIN_SELECT entered");
|
`INTEST : $write("\n\tInstruction INTEST");
|
`INTEST : $write("\tInstruction INTEST entered");
|
`CLAMP : $write("\n\tInstruction CLAMP");
|
`CLAMP : $write("\tInstruction CLAMP entered");
|
`CLAMPZ : $write("\n\tInstruction CLAMPZ");
|
`CLAMPZ : $write("\tInstruction CLAMPZ entered");
|
`HIGHZ : $write("\n\tInstruction HIGHZ");
|
`HIGHZ : $write("\tInstruction HIGHZ entered");
|
`DEBUG : $write("\n\tInstruction DEBUG");
|
`DEBUG : $write("\tInstruction DEBUG entered");
|
`BYPASS : $write("\n\tInstruction BYPASS");
|
`BYPASS : $write("\tInstruction BYPASS entered");
|
default : $write("\n\tInstruction not valid. Instruction BYPASS activated !!!");
|
default : $write("\n\tInstruction not valid. Instruction BYPASS activated !!!");
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
Line 828... |
Line 905... |
always @ (posedge P_TCK)
|
always @ (posedge P_TCK)
|
begin
|
begin
|
if(dbg_tb.i_tap_top.CHAIN_SELECTSelected & dbg_tb.i_tap_top.UpdateDR_q)
|
if(dbg_tb.i_tap_top.CHAIN_SELECTSelected & dbg_tb.i_tap_top.UpdateDR_q)
|
case(dbg_tb.i_dbg_top.Chain[`CHAIN_ID_LENGTH-1:0])
|
case(dbg_tb.i_dbg_top.Chain[`CHAIN_ID_LENGTH-1:0])
|
`GLOBAL_BS_CHAIN : $write("\nChain GLOBAL_BS_CHAIN");
|
`GLOBAL_BS_CHAIN : $write("\nChain GLOBAL_BS_CHAIN");
|
`RISC_DEBUG_CHAIN_2 : $write("\nChain RISC_DEBUG_CHAIN_2");
|
`CPU_DEBUG_CHAIN_0 : $write("\nChain CPU_DEBUG_CHAIN_0");
|
`RISC_TEST_CHAIN : $write("\nChain RISC_TEST_CHAIN");
|
`CPU_DEBUG_CHAIN_1 : $write("\nChain CPU_DEBUG_CHAIN_1");
|
|
`CPU_DEBUG_CHAIN_2 : $write("\nChain CPU_DEBUG_CHAIN_2");
|
|
`CPU_DEBUG_CHAIN_3 : $write("\nChain CPU_DEBUG_CHAIN_3");
|
|
`CPU_TEST_CHAIN : $write("\nChain CPU_TEST_CHAIN");
|
`TRACE_TEST_CHAIN : $write("\nChain TRACE_TEST_CHAIN");
|
`TRACE_TEST_CHAIN : $write("\nChain TRACE_TEST_CHAIN");
|
`REGISTER_SCAN_CHAIN : $write("\nChain REGISTER_SCAN_CHAIN");
|
`REGISTER_SCAN_CHAIN : $write("\nChain REGISTER_SCAN_CHAIN");
|
`WISHBONE_SCAN_CHAIN : $write("\nChain WISHBONE_SCAN_CHAIN");
|
`WISHBONE_SCAN_CHAIN : $write("\nChain WISHBONE_SCAN_CHAIN");
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
// print RISC registers read/write
|
// print CPU registers read/write
|
always @ (posedge Mclk)
|
always @ (posedge Mclk)
|
begin
|
begin
|
if(dbg_tb.i_dbg_top.RISCAccess & ~dbg_tb.i_dbg_top.RISCAccess_q & dbg_tb.i_dbg_top.RW)
|
if(dbg_tb.i_dbg_top.CPUAccess0 & ~dbg_tb.i_dbg_top.CPUAccess_q & dbg_tb.i_dbg_top.RW)
|
$write("\n\t\tWrite to RISC Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[31:0], dbg_tb.i_dbg_top.DataOut[31:0]);
|
$write("\n\t\tWrite to CPU Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[31:0], dbg_tb.i_dbg_top.DataOut[31:0]);
|
else
|
else
|
if(dbg_tb.i_dbg_top.RISCAccess_q & ~dbg_tb.i_dbg_top.RISCAccess_q2 & ~dbg_tb.i_dbg_top.RW)
|
if(dbg_tb.i_dbg_top.CPUAccess_q & ~dbg_tb.i_dbg_top.CPUAccess_q2 & ~dbg_tb.i_dbg_top.RW)
|
$write("\n\t\tRead from RISC Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[31:0], dbg_tb.i_dbg_top.risc_data_i[31:0]);
|
$write("\n\t\tRead from CPU Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[31:0], dbg_tb.i_dbg_top.cpu_data_i[31:0]);
|
end
|
end
|
|
|
|
|
// print registers read/write
|
// print registers read/write
|
always @ (posedge Mclk)
|
always @ (posedge Mclk)
|
Line 863... |
Line 943... |
end
|
end
|
|
|
|
|
// print CRC error
|
// print CRC error
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
wire CRCErrorReport = ~(dbg_tb.i_dbg_top.CrcMatch & (dbg_tb.i_dbg_top.CHAIN_SELECTSelected | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.RegisterScanChain | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.RiscDebugScanChain | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.TraceTestScanChain | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.WishboneScanChain));
|
wire CRCErrorReport = ~(dbg_tb.i_dbg_top.CrcMatch & (dbg_tb.i_dbg_top.CHAIN_SELECTSelected | dbg_tb.i_dbg_top.DEBUGSelected & RegisterScanChain | dbg_tb.i_dbg_top.DEBUGSelected & (CpuDebugScanChain0 | CpuDebugScanChain1 | CpuDebugScanChain2 | CpuDebugScanChain3) | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.TraceTestScanChain | dbg_tb.i_dbg_top.DEBUGSelected & WishboneScanChain));
|
`else // TRACE_ENABLED not enabled
|
`else // TRACE_ENABLED not enabled
|
wire CRCErrorReport = ~(dbg_tb.i_dbg_top.CrcMatch & (dbg_tb.i_tap_top.CHAIN_SELECTSelected | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.RegisterScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.RiscDebugScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.WishboneScanChain));
|
wire CRCErrorReport = ~(dbg_tb.i_dbg_top.CrcMatch & (dbg_tb.i_tap_top.CHAIN_SELECTSelected | dbg_tb.i_tap_top.DEBUGSelected & RegisterScanChain | dbg_tb.i_tap_top.DEBUGSelected & (CpuDebugScanChain0 | CpuDebugScanChain1 | CpuDebugScanChain2 | CpuDebugScanChain3) | dbg_tb.i_tap_top.DEBUGSelected & WishboneScanChain));
|
`endif
|
`endif
|
|
|
always @ (posedge P_TCK)
|
always @ (posedge P_TCK)
|
begin
|
begin
|
if(dbg_tb.i_tap_top.UpdateDR & ~dbg_tb.i_tap_top.IDCODESelected)
|
if(dbg_tb.i_tap_top.UpdateDR & ~dbg_tb.i_tap_top.IDCODESelected)
|
begin
|
begin
|
if(dbg_tb.i_tap_top.CHAIN_SELECTSelected)
|
if(dbg_tb.i_tap_top.CHAIN_SELECTSelected)
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$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[11:4], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
|
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[11:4], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
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else
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else
|
if(dbg_tb.i_tap_top.RegisterScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
|
if(RegisterScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
|
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[45:38], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
|
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[45:38], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
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else
|
else
|
if(dbg_tb.i_tap_top.RiscDebugScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
|
if((CpuDebugScanChain0 | CpuDebugScanChain1 | CpuDebugScanChain2 | CpuDebugScanChain3) & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
|
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
|
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
|
if(dbg_tb.i_tap_top.WishboneScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
|
if(WishboneScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
|
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
|
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
|
|
|
if(CRCErrorReport)
|
if(CRCErrorReport)
|
begin
|
begin
|
$write("\n\t\t\t\tCrc Error when receiving data (read or write) !!! CrcIn should be: 0x%h\n", dbg_tb.i_dbg_top.CalculatedCrcIn);
|
$write("\n\t\t\t\tCrc Error when receiving data (read or write) !!! CrcIn should be: 0x%h\n", dbg_tb.i_dbg_top.CalculatedCrcIn);
|
#1000 $stop;
|
#1000 $stop;
|
end
|
end
|
|
$display("\n");
|
end
|
end
|
end
|
end
|
|
|
|
|
// Print shifted IDCode
|
// Print shifted IDCode
|
Line 902... |
Line 983... |
begin
|
begin
|
if(dbg_tb.i_tap_top.ShiftDR)
|
if(dbg_tb.i_tap_top.ShiftDR)
|
TempData[31:0]<=#Tp {dbg_tb.i_tap_top.tdo_pad_o, TempData[31:1]};
|
TempData[31:0]<=#Tp {dbg_tb.i_tap_top.tdo_pad_o, TempData[31:1]};
|
else
|
else
|
if(dbg_tb.i_tap_top.UpdateDR)
|
if(dbg_tb.i_tap_top.UpdateDR)
|
|
if (TempData[31:0] != `IDCODE_VALUE)
|
|
begin
|
|
$display("(%0t) ERROR: IDCODE not correct", $time);
|
|
$stop;
|
|
end
|
|
else
|
$write("\n\t\tIDCode = 0x%h", TempData[31:0]);
|
$write("\n\t\tIDCode = 0x%h", TempData[31:0]);
|
end
|
end
|
end
|
end
|
|
|
|
|
Line 922... |
Line 1009... |
$write("\n\t\TraceData = 0x%h + Crc = 0x%h", TraceData[39:0], TraceData[47:40]);
|
$write("\n\t\TraceData = 0x%h + Crc = 0x%h", TraceData[39:0], TraceData[47:40]);
|
end
|
end
|
end
|
end
|
|
|
|
|
|
// We never use following states: Exit2IR, Exit2DR, PauseIR or PauseDR
|
|
always @ (posedge P_TCK)
|
|
begin
|
|
if(dbg_tb.i_tap_top.Exit2IR | dbg_tb.i_tap_top.Exit2DR | dbg_tb.i_tap_top.PauseIR | dbg_tb.i_tap_top.PauseDR)
|
|
begin
|
|
$display("\n(%0t) ERROR: Exit2IR, Exit2DR, PauseIR or PauseDR state detected.", $time);
|
|
$display("(%0t) Simulation stopped !!!", $time);
|
|
$stop;
|
|
end
|
|
end
|
|
|
|
|
|
|
|
|
|
|
|
|
endmodule // TB
|
endmodule // TB
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No newline at end of file
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No newline at end of file
|