URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_15/] [bench/] [verilog/] [dbg_tb_defines.v] - Diff between revs 2 and 5

Rev 2	Rev 5
Line 43...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
	`// Initial official release.`
	`//`
`// Revision 1.3 2001/06/01 22:23:40 mohor`	`// Revision 1.3 2001/06/01 22:23:40 mohor`
`// This is a backup. It is not a fully working version. Not for use, yet.`	`// This is a backup. It is not a fully working version. Not for use, yet.`
`//`	`//`
`// Revision 1.2 2001/05/18 13:10:05 mohor`	`// Revision 1.2 2001/05/18 13:10:05 mohor`
`// Headers changed. All additional information is now avaliable in the README.txt file.`	`// Headers changed. All additional information is now avaliable in the README.txt file.`
Line 57...	Line 60...
`//`	`//`

`// Following defines are used in the testbench only`	`// Following defines are used in the testbench only`

`// MODER register`	`// MODER register`
`define CONTIN 32'h00000001	`define ENABLE 32'h00010000
`define ENABLE 32'h00000002	`define CONTIN 32'h00020000

`// TSEL register`	`// TSEL register`
`define WPTRIG_0 32'h00000001	`define WPTRIG_0 32'h00000001
`define WPTRIG_1 32'h00000002	`define WPTRIG_1 32'h00000002
`define WPTRIG_2 32'h00000004	`define WPTRIG_2 32'h00000004