| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2004/01/16 14:53:31 mohor
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// *** empty log message ***
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//
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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| Line 66... |
Line 69... |
cpu_ce_i,
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cpu_ce_i,
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crc_match_i,
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crc_match_i,
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crc_en_o,
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crc_en_o,
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shift_crc_o,
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shift_crc_o,
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rst_i,
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rst_i,
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clk_i
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// CPU signals
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cpu_clk_i,
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cpu_addr_o,
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cpu_data_i,
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cpu_data_o,
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cpu_bp_i,
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cpu_stall_o,
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cpu_stall_all_o,
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cpu_stb_o,
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cpu_sel_o, // Not synchronized
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cpu_we_o,
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cpu_ack_i,
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cpu_rst_o
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);
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);
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// JTAG signals
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// JTAG signals
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| Line 86... |
Line 102... |
input cpu_ce_i;
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input cpu_ce_i;
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input crc_match_i;
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input crc_match_i;
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output crc_en_o;
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output crc_en_o;
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output shift_crc_o;
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output shift_crc_o;
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input rst_i;
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input rst_i;
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input clk_i;
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// CPU signals
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input cpu_clk_i;
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output [31:0] cpu_addr_o;
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input [31:0] cpu_data_i;
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output [31:0] cpu_data_o;
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input cpu_bp_i;
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output cpu_stall_o;
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output cpu_stall_all_o;
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output cpu_stb_o;
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output [`CPU_NUM -1:0] cpu_sel_o;
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output cpu_we_o;
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input cpu_ack_i;
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output cpu_rst_o;
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reg tdo_o;
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reg tdo_o;
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wire cmd_cnt_en;
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wire cmd_cnt_en;
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reg [1:0] cmd_cnt;
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reg [1:0] cmd_cnt;
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| Line 114... |
Line 146... |
reg [3:0] status;
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reg [3:0] status;
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wire enable;
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wire enable;
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reg read_cycle_reg;
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reg read_cycle_reg;
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reg read_cycle_reg_q;
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reg read_cycle_cpu;
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reg read_cycle_cpu;
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reg read_cycle_cpu_q;
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reg write_cycle_reg;
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reg write_cycle_reg;
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reg write_cycle_cpu;
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reg write_cycle_cpu;
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wire read_cycle;
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wire read_cycle;
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wire write_cycle;
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wire write_cycle;
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reg [34:0] dr;
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reg [34:0] dr;
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wire [7:0] reg_data_out;
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wire dr_read_reg;
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wire dr_read_reg;
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wire dr_write_reg;
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wire dr_write_reg;
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wire dr_read_cpu8;
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wire dr_read_cpu8;
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wire dr_read_cpu32;
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wire dr_read_cpu32;
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| Line 142... |
Line 177... |
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reg cmd_read_reg;
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reg cmd_read_reg;
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reg cmd_read_cpu;
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reg cmd_read_cpu;
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reg cmd_write_reg;
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reg cmd_write_reg;
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reg cmd_write_cpu;
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reg cmd_write_cpu;
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reg cycle_32_bit;
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reg reg_access;
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reg [31:0] adr;
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reg set_addr;
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reg [199:0] latching_data_text;
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reg cpu_ack_sync;
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reg cpu_ack_tck;
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reg cpu_ack_tck_q;
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reg cpu_stb;
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reg cpu_stb_sync;
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reg cpu_stb_o;
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wire go_prelim;
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wire go_prelim;
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wire crc_cnt_31;
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wire crc_cnt_31;
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assign enable = cpu_ce_i & shift_dr_i;
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assign enable = cpu_ce_i & shift_dr_i;
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assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
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assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
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assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
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assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
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| Line 279... |
Line 327... |
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assign status_cnt_end = status_cnt4;
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assign status_cnt_end = status_cnt4;
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reg [31:0] adr;
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reg set_addr;
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// Latching address
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// Latching address
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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| Line 299... |
Line 345... |
else
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else
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set_addr <= #1 1'b0;
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set_addr <= #1 1'b0;
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end
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end
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reg latch_data;
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assign cpu_addr_o = adr;
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reg [199:0] latching_data_text;
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// Shift register for shifting in and out the data
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// Shift register for shifting in and out the data
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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if (enable & ((~addr_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle)))
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if (reg_access)
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begin
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dr[31:24] <= #1 reg_data_out;
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latching_data_text = "Latch reg data";
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end
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else if (cpu_ack_tck & (~cpu_ack_tck_q) & read_cycle_cpu)
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begin
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if (cycle_32_bit)
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dr[31:0] <= #1 cpu_data_i;
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else
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dr[31:24] <= #1 cpu_data_i[7:0];
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latching_data_text = "Latch cpu data";
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end
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else if (enable & ((~addr_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle) | (crc_cnt_end & (~data_cnt_end) & read_cycle)))
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begin
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begin
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dr <= #1 {dr[33:0], tdi_i};
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dr <= #1 {dr[33:0], tdi_i};
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latch_data <= #1 1'b0;
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latching_data_text = "shifting data";
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latching_data_text = "tdi shifted in";
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end
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end
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else
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else
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latching_data_text = "nothing";
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latching_data_text = "nothing";
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end
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end
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Line 417... |
begin
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begin
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cmd_read_reg <= #1 1'b0;
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cmd_read_reg <= #1 1'b0;
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cmd_read_cpu <= #1 1'b0;
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cmd_read_cpu <= #1 1'b0;
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cmd_write_reg <= #1 1'b0;
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cmd_write_reg <= #1 1'b0;
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cmd_write_cpu <= #1 1'b0;
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cmd_write_cpu <= #1 1'b0;
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cycle_32_bit <= #1 1'b0;
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end
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end
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else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
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else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
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begin
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begin
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cmd_read_reg <= #1 dr_read_reg_latched;
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cmd_read_reg <= #1 dr_read_reg_latched;
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cmd_read_cpu <= #1 dr_read_cpu8_latched | dr_read_cpu32_latched;
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cmd_read_cpu <= #1 dr_read_cpu8_latched | dr_read_cpu32_latched;
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cmd_write_reg <= #1 dr_write_reg_latched;
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cmd_write_reg <= #1 dr_write_reg_latched;
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cmd_write_cpu <= #1 dr_write_cpu8_latched | dr_write_cpu32_latched;
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cmd_write_cpu <= #1 dr_write_cpu8_latched | dr_write_cpu32_latched;
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cycle_32_bit <= #1 dr_read_cpu32_latched | dr_write_cpu32_latched;
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end
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end
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end
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end
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// Upper limit. Data counter counts until this value is reached.
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// Upper limit. Data counter counts until this value is reached.
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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data_cnt_limit <= #1 6'h0;
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data_cnt_limit <= #1 6'h0;
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else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
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else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (~dr_go_latched))
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begin
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begin
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if (dr_read_cpu32_latched | dr_write_cpu32_latched)
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if (dr_read_cpu32_latched | dr_write_cpu32_latched)
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data_cnt_limit <= #1 6'd32;
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data_cnt_limit <= #1 6'd32;
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else
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else
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data_cnt_limit <= #1 6'd8;
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data_cnt_limit <= #1 6'd8;
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Line 468... |
end
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end
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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read_cycle_reg_q <= #1 read_cycle_reg;
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read_cycle_cpu_q <= #1 read_cycle_cpu;
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end
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always @ (posedge tck_i)
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begin
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if (update_dr_i)
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if (update_dr_i)
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write_cycle_reg <= #1 1'b0;
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write_cycle_reg <= #1 1'b0;
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else if (cmd_write_reg & go_prelim)
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else if (cmd_write_reg & go_prelim)
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write_cycle_reg <= #1 1'b1;
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write_cycle_reg <= #1 1'b1;
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end
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end
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Line 494... |
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assign read_cycle = read_cycle_reg | read_cycle_cpu;
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assign read_cycle = read_cycle_reg | read_cycle_cpu;
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assign write_cycle = write_cycle_reg | write_cycle_cpu;
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assign write_cycle = write_cycle_reg | write_cycle_cpu;
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reg reg_access;
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// Start register write cycle
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// Start register access cycle
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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if (write_cycle_reg & data_cnt_end & (~data_cnt_end_q))
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if (write_cycle_reg & data_cnt_end & (~data_cnt_end_q) | read_cycle_reg & (~read_cycle_reg_q))
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begin
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begin
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reg_access <= #1 1'b1;
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reg_access <= #1 1'b1;
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end
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end
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else
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else
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reg_access <= #1 1'b0;
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reg_access <= #1 1'b0;
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Line 512... |
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// Connecting dbg_cpu_registers
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// Connecting dbg_cpu_registers
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dbg_cpu_registers i_dbg_cpu_registers
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dbg_cpu_registers i_dbg_cpu_registers
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(
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(
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.data_in (dr[7:0]),
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.data_i (dr[7:0]),
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.data_out (),
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.data_o (reg_data_out),
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.address (adr[1:0]),
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.addr_i (adr[1:0]),
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.rw (write_cycle),
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.we_i (write_cycle_reg),
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.access (reg_access),
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.en_i (reg_access),
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.clk (tck_i),
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.clk_i (tck_i),
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.bp (1'b1),
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.bp_i (cpu_bp_i),
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.reset (rst_i),
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.rst_i (rst_i),
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.cpu_stall (),
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.cpu_clk_i (cpu_clk_i),
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.cpu_stall_all (),
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.cpu_stall_o (cpu_stall_o),
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.cpu_sel (),
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.cpu_stall_all_o (cpu_stall_all_o),
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.cpu_reset ()
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.cpu_sel_o (cpu_sel_o),
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.cpu_rst_o (cpu_rst_o)
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);
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);
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assign cpu_we_o = write_cycle_cpu;
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assign cpu_data_o = dr[31:0];
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// Synchronizing ack signal from cpu
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always @ (posedge tck_i)
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begin
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cpu_ack_sync <= #1 cpu_ack_i;
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cpu_ack_tck <= #1 cpu_ack_sync;
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cpu_ack_tck_q <= #1 cpu_ack_tck;
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end
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// Start cpu access cycle
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always @ (posedge tck_i)
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begin
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if (update_dr_i)
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cpu_stb <= #1 1'b0;
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else if (cpu_ack_tck)
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cpu_stb <= #1 1'b0;
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else if (write_cycle_cpu & data_cnt_end & (~data_cnt_end_q) | read_cycle_cpu & (~read_cycle_cpu_q))
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cpu_stb <= #1 1'b1;
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end
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always @ (posedge tck_i)
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begin
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cpu_stb_sync <= #1 cpu_stb;
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cpu_stb_o <= #1 cpu_stb_sync;
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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