| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2004/01/17 17:01:14 mohor
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// Almost finished.
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//
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// Revision 1.1 2004/01/16 14:53:31 mohor
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// Revision 1.1 2004/01/16 14:53:31 mohor
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// *** empty log message ***
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// *** empty log message ***
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//
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//
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//
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//
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//
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//
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| Line 121... |
Line 124... |
output cpu_rst_o;
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output cpu_rst_o;
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reg tdo_o;
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reg tdo_o;
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reg [799:0] tdo_text;
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wire cmd_cnt_en;
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wire cmd_cnt_en;
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reg [1:0] cmd_cnt;
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reg [1:0] cmd_cnt;
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wire cmd_cnt_end;
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wire cmd_cnt_end;
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reg cmd_cnt_end_q;
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reg cmd_cnt_end_q;
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| Line 142... |
Line 146... |
wire data_cnt_end;
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wire data_cnt_end;
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reg data_cnt_end_q;
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reg data_cnt_end_q;
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wire status_cnt_end;
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wire status_cnt_end;
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reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;
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reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;
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reg [3:0] status;
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reg [3:0] status;
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reg [199:0] status_text;
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reg crc_match_reg;
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wire enable;
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wire enable;
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reg read_cycle_reg;
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reg read_cycle_reg;
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reg read_cycle_reg_q;
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reg read_cycle_reg_q;
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reg read_cycle_cpu;
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reg read_cycle_cpu;
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| Line 558... |
Line 564... |
cpu_stb <= #1 1'b1;
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cpu_stb <= #1 1'b1;
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end
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end
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always @ (posedge tck_i)
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// Synchronizing cpu_stb to cpu_clk_i clock
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always @ (posedge cpu_clk_i)
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begin
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begin
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cpu_stb_sync <= #1 cpu_stb;
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cpu_stb_sync <= #1 cpu_stb;
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cpu_stb_o <= #1 cpu_stb_sync;
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cpu_stb_o <= #1 cpu_stb_sync;
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end
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end
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// Latching crc
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always @ (posedge tck_i)
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begin
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if(crc_cnt_end & (~crc_cnt_end_q))
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crc_match_reg <= #1 crc_match_i;
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end
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// Status register
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always @ (posedge tck_i or posedge rst_i)
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begin
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if (rst_i)
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begin
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status <= #1 'h0;
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status_text <= #1 "reset";
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end
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else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
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begin
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status <= #1 {crc_match_i, 1'b0, 1'b1, 1'b0};
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status_text <= #1 "!!!READ";
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end
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else if (data_cnt_end & (~data_cnt_end_q) & read_cycle)
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begin
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status <= #1 {crc_match_reg, 1'b0, 1'b1, 1'b0};
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status_text <= #1 "READ";
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end
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else if (shift_dr_i & (~status_cnt_end))
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begin
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status <= #1 {status[0], status[3:1]};
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status_text <= #1 "shift";
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end
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end
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// Following status is shifted out:
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// 1. bit: 1 if crc is OK, else 0
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// 2. bit: 1'b0
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// 3. bit: 1'b1
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// 4. bit: 1'b0
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// TDO multiplexer
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always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or data_cnt_end or data_cnt_end_q or
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read_cycle or crc_match_reg or status or dr)
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begin
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if (crc_cnt_end & (~crc_cnt_end_q) & (~(read_cycle)))
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begin
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tdo_o = crc_match_i;
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tdo_text = "crc_match_i";
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end
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else if (read_cycle & crc_cnt_end & (~data_cnt_end))
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begin
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tdo_o = dr[31];
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tdo_text = "read data";
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end
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else if (read_cycle & data_cnt_end & (~data_cnt_end_q)) // cmd is already updated
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begin
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tdo_o = crc_match_reg;
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tdo_text = "crc_match_reg";
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end
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else if (crc_cnt_end)
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begin
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tdo_o = status[0];
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tdo_text = "status";
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end
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else
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begin
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tdo_o = 1'b0;
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tdo_text = "zero while CRC is shifted in";
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end
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end
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endmodule
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endmodule
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