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//// ////
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//// ////
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//// dbg_defines.v ////
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//// dbg_defines.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// http://www.opencores.org/cores/DebugInterface/ ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000,2001 Authors ////
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//// Copyright (C) 2000 - 2003 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.14 2003/10/23 16:17:00 mohor
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// CRC logic changed.
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//
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// Revision 1.13 2003/10/21 09:48:31 simons
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// Revision 1.13 2003/10/21 09:48:31 simons
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// Mbist support added.
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// Mbist support added.
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//
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//
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// Revision 1.12 2003/09/17 14:38:57 simons
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// Revision 1.12 2003/09/17 14:38:57 simons
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// WB_CNTL register added, some syncronization fixes.
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// WB_CNTL register added, some syncronization fixes.
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// Initial release
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// Initial release
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//
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//
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//
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//
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// Enable TRACE
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//`define TRACE_ENABLED // Uncomment this define to activate the trace
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// Define number of cpus supported by the dbg interface
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`define CPU_NUM 2
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// Define IDCODE Value
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`define IDCODE_VALUE 32'h14951185
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// Define master clock (CPU clock)
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//`define CPU_CLOCK 50 // Half period = 50 ns => MCLK = 10 Mhz
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`define CPU_CLOCK 2.5 // Half period = 5 ns => MCLK = 200 Mhz
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// Length of the Instruction register
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`define IR_LENGTH 4
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// Length of the Data register (must be equal to the longest scan chain for shifting the data in)
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`define DR_LENGTH 74
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// Length of the CHAIN ID register
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// Length of the CHAIN ID register
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`define CHAIN_ID_LENGTH 4
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`define CHAIN_ID_LENGTH 3
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// Length of the CRC
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// Length of data
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`define CRC_LENGTH 8
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`define CHAIN_DATA_LEN `CHAIN_ID_LENGTH + 1
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`define DATA_CNT 3
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// Length of status
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`define STATUS_LEN 4
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`define STATUS_CNT 3
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// Trace buffer size and counter and write/read pointer width. This can be expanded when more RAM is avaliable
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// Length of the CRC
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`define TRACECOUNTERWIDTH 5
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`define CRC_LEN 32
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`define TRACEBUFFERLENGTH 32 // 2^5
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`define CRC_CNT 6
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`define TRACESAMPLEWIDTH 36
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// OpSelect width
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`define OPSELECTWIDTH 3
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`define OPSELECTIONCOUNTER 8 //2^3
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// OpSelect (dbg_op_i) signal meaning
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`define DEBUG_READ_0 0
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`define DEBUG_WRITE_0 1
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`define DEBUG_READ_1 2
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`define DEBUG_WRITE_1 3
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`define DEBUG_READ_2 4
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`define DEBUG_WRITE_2 5
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`define DEBUG_READ_3 6
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`define DEBUG_WRITE_3 7
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// Supported Instructions
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`define EXTEST 4'b0000
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`define SAMPLE_PRELOAD 4'b0001
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`define IDCODE 4'b0010
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`define CHAIN_SELECT 4'b0011
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`define INTEST 4'b0100
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`define CLAMP 4'b0101
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`define CLAMPZ 4'b0110
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`define HIGHZ 4'b0111
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`define DEBUG 4'b1000
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`define MBIST 4'b1001
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`define BYPASS 4'b1111
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// Chains
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// Chains
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`define GLOBAL_BS_CHAIN 4'b0000
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`define CPU_DEBUG_CHAIN 3'b000
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`define CPU_DEBUG_CHAIN_2 4'b0001
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`define WISHBONE_SCAN_CHAIN 3'b001
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`define CPU_TEST_CHAIN 4'b0010
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`define TRACE_TEST_CHAIN 4'b0011
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`define REGISTER_SCAN_CHAIN 4'b0100
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`define WISHBONE_SCAN_CHAIN 4'b0101
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`define CPU_DEBUG_CHAIN_0 4'b0110
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`define CPU_DEBUG_CHAIN_1 4'b0111
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`define CPU_DEBUG_CHAIN_3 4'b1000
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// Registers addresses
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`define MODER_ADR 5'h00
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`define TSEL_ADR 5'h01
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`define QSEL_ADR 5'h02
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`define SSEL_ADR 5'h03
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`define CPUOP_ADR 5'h04
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`define CPUSEL_ADR 5'h05
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`define RECSEL_ADR 5'h10
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`define MON_CNTL_ADR 5'h11
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`define WB_CNTL_ADR 5'h12
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// Registers default values (after reset)
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`define MODER_DEF 2'h0
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`define TSEL_DEF 32'h00000000
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`define QSEL_DEF 32'h00000000
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`define SSEL_DEF 32'h00000000
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`define CPUOP_DEF 2'h0
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`define RECSEL_DEF 7'h0
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`define MON_CNTL_DEF 4'h0
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No newline at end of file
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No newline at end of file
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